Abstract: A method for functionalizing a hollow-fiber membrane for cell expansion of targeted cells (e.g., natural killer cells) includes contacting a biotinylating molecule to a surface of the hollow-fiber membrane including an extracellular matrix component, the biotinylating molecule binding to the extracellular matrix component and having an affinity for the targeted cells. The biotinylated molecule may be selected from the group consisting of: cytokine, epitope, ligand, monoclonal antibody, stains, aptamer, and combinations thereof. The extracellular matrix component may be selected from the group consisting of: fibronectin, vitronectin, fibrinogen, collagen, laminin, and combinations thereof.

Abstract: A multilayer substrate having a bonding surface is disclosed. One embodiment of the substrate may comprise a bypass capacitor connection pad disposed on the bonding surface. The bypass capacitor connection pad may have a bypass capacitor power pad and a bypass capacitor ground pad. The substrate may also comprise a plurality of power vias routed from the bypass capacitor power pad to a first redistribution layer spaced apart from the bonding surface and a plurality of ground vias routed from the bypass capacitor ground pad to the first redistribution layer. The substrate may further comprise a plurality of power and ground vias routed from the first redistribution layer to a second redistribution layer according to a power and ground via pattern array, wherein the plurality of ground vias are jogged at the first redistribution layer to the plurality of power vias to form the power and ground via pattern array.

Abstract: A method for routing vias in a multilayer substrate is disclosed. One embodiment of a method may comprise providing a multilayer substrate with an internal bond surface having a plurality of internal bond pads and an external bond surface with a plurality of external bond pads. A plurality of power vias and ground vias may be routed from a first redistribution layer between the internal bond surface and the external bond surface to a second redistribution layer between the first redistribution layer and the external bond surface based on a via pattern. The via pattern may comprise routing a power via and a ground via adjacent one another spaced apart at a distance that is substantially equal to a minimum routing pitch associated with the multilayer substrate.

Abstract: A method and software product evaluate vias in an electronic design. One or more via sufficiency rules are formulated, and then the electronic design is processed to determine whether the vias of the electronic design violate the via sufficiency rules. In the event of a violation, one or more indicators are generated to identify vias that violate the via sufficiency rules. The indicators are visual indicators (e.g., via insufficiency DRCs) on a graphical user interface, and/or a textual report summarizing violations.

Abstract: Systems and methods associated with generating node level bypass capacitor models are disclosed. One embodiment of a system may comprise a plurality of bypass capacitor circuit models associated with respective bypass capacitors and a node level model generator. The node level model generator may associate bypass capacitor information for a plurality of bypass capacitors from a data base associated with a multi-layer structure design with respective bypass capacitor circuit models to provide a node level capacitor model for the plurality of bypass capacitors.

Abstract: Systems and methods for determining a signal coupling coefficient for a line or trace in an electrical circuit layout are disclosed. The systems and methods include, for example, reading a threshold value for a signal coupling coefficient, identifying the line in a circuit design database, establishing a window around the line in which circuit elements will be included in a calculation of the signal coupling coefficient of the line, calculating a signal coupling coefficient of the line based upon the circuit elements in the window, flagging the line if the calculated coupling coefficient differs from the threshold value, flagging the target line with a design rule check if the threshold value exceeds the calculated coefficient and storing the design rule check in the circuit design database. Systems and methods for determining signal coupling coefficients for one or more vias or paths are also disclosed.

Abstract: A method is provided for evaluating trace signal coupling in an electronic design (e.g., a package design). In the method, one or more trace signal coupling rules are formulated. One or more trace pairs designed to carry differential signals are then processed to determine whether the inter-trace spacing between the trace pairs violates the trace signal coupling rules. An indicator (e.g., a DRC and/or a report) is generated to identify violated trace signal coupling rules. Processing of the electronic design may be scoped according one or a group of signal nets, or one or a group of levels of the package design.

Abstract: A method for routing signals in a multilayer substrate is disclosed. One embodiment of a method may comprise providing a multilayer substrate with at least one differential signal line pair aligned along a common plane that is substantially transverse to a top surface of the multilayer substrate, jogging a first differential signal line associated with a differential signal line pair at a first redistribution layer in a direction along the common plane, and jogging a second differential signal line associated with the differential signal line pair at a second redistribution layer along the common plane in a same direction as the first differential signal line to provide a substantially balanced differential signal line pair.

Abstract: A method for routing vias in a multilayer substrate from bypass capacitor pads is disclosed. One embodiment of a method may comprise arranging a bypass capacitor power pad spaced apart from a bypass capacitor ground pad on a first surface of the multilayer substrate, routing a plurality of power vias from the bypass capacitor power pad to a first redistribution layer spaced from the first surface, and routing a plurality of ground vias from the bypass capacitor ground pad to the first redistribution layer. The methodology may further comprise jogging the plurality of ground vias at the first redistribution layer to the plurality of power vias to provide a power and ground via pattern, and routing the power and ground vias from the first redistribution layer to a second redistribution layer spaced apart from the first redistribution layer based on the power and ground via pattern.

Abstract: According to at least one embodiment, a method comprises generating a data file having design parameters for an electrical design, and with a computer-executable program, accessing the data file and populating a computer-aided design (CAD) program's database with the design parameters.

Abstract: A method is provided for evaluating signal deviations in an electronic design (e.g., a package design), including the steps of: formulating one or more signal deviation rules; processing the electronic design to determine whether the signal deviations violate the signal deviation rules; and generating an indicator (e.g., a DRC and/or report) associated with the electronic design to identify violated signal deviation rules. Processing of the electronic design may be scoped according one or a group of signal nets.

Abstract: A computer-implemented method is disclosed for adjusting impedance. A list of differential line pairs in a circuit design database is searched through for a target differential line pair, where the target differential line pair is flagged as having an incorrect characteristic impedance. A position in a circuit layout described in said circuit design database of at least one line in the differential line pair is adjusted to correct the characteristic impedance.

Abstract: A computer-implemented method is disclosed for adjusting impedance of a differential via pair in an electrical circuit layout. A differential via pair having an odd mode characteristic impedance needing adjustment is identified in a circuit design database. A region is established around the differential via pair in which circuit elements may be modified to adjust the odd mode characteristic impedance of the differential via pair. At least one of the circuit elements in the electrical circuit layout in the established region is adjusted until the odd mode characteristic impedance is closer to a desired odd mode characteristic impedance value.

Abstract: A computer-implemented method is disclosed for verifying signal via impedance. Properties of a signal via and of any other vias within a given distance of the signal via are read from a circuit design database. A target characteristic impedance value for the signal via is obtained. A characteristic impedance of the signal via is calculated based on the other vias. The signal via is flagged as having an incorrect characteristic impedance if the calculated characteristic impedance does not match the target characteristic impedance value.

Abstract: A computer-implemented method for adjusting impedance is disclosed. A desired impedance value for a signal line in an electrical circuit layout is read, and the signal line is identified in a circuit design database. A window is established around the signal line in which circuit elements will be included in an impedance adjustment for the signal line. The impedance adjustment is performed by adjusting at least one of the circuit elements in the window to bring an impedance of the signal line nearer the desired impedance value.

Abstract: A computer-implemented method is disclosed for verifying differential line pair impedance. Properties for a differential line pair segment are read from a circuit design database. Properties of neighboring traces are also from the circuit design database, with the neighboring traces being within a given distance of the differential line pair segment. A modal characteristic impedance of the differential line pair segment is calculated based on the neighboring traces. The differential line pair segment is flagged as having an improper impedance value if the calculated modal characteristic impedance differs from a desired modal characteristic impedance.

Abstract: A method evaluates signal trace discontinuities in an electronic design of the type having one or more traces. The method includes the steps of formulating one or more trace discontinuity rules, processing the electronic design to determine whether the traces violate the trace discontinuity rules, and generating an indicator (e.g., a DRC) associated with the electronic design to identify violated trace discontinuity rules. Each level, each signal net, or a group of signal nets may be evaluated, for example, to ensure compliance with the trace discontinuity rules.

Abstract: Techniques are disclosed for verifying the proximity of ground vias to signal vias in an integrated circuit package design. A package designer creates the package design using a package design tool. A proximity verifier verifies that there is a ground via within a predetermined threshold distance of each specified signal via in the package design. The proximity verifier may notify the package designer of any signal vias which are not sufficiently close to ground vias, such as by providing visual indications of such signal vias in a graphical representation of the package design displayed on a display monitor. In response, the package designer may modify the package model to ensure that all signal vias are sufficiently close to ground vias. The proximity verifier may be implemented as a design rule which may be executed automatically and in real-time by the package design tool.

Abstract: A method and software product evaluate vias, per pad, in an electronic design. One or more via per pad rules are formulated, and then the electronic design is processed to determine whether the vias of the electronic design violate the via per pad rules. In the event of a violation, one or more indicators are generated to identify vias that violate the via per pad rules. The indicators are visual indicators (e.g., via per pad DRCs) on a graphical user interface, and/or a textual report summarizing violations.

Abstract: A computer-implemented method is disclosed for verifying impedance in a differential via pair. A target differential via pair is identified in a design database. A desired modal characteristic impedance for the target differential via pair is obtained. A two-dimensional window is established around the differential via pair in which neighboring vias will be included in a modal characteristic impedance calculation for the target differential via pair. A modal characteristic impedance for the target differential via pair is calculated based at least in part on the neighboring vias in the two-dimensional window. The target differential via pair is flagged if the calculated modal characteristic impedance does not match the desired modal characteristic impedance.