Abstract: In a video processing system, a method and system for dynamically configurable DCT/IDCT module in a wireless handset are provided. A processor may be used to configure a quantization scheme and video format mode of operation and to configure a processing network in a DCT/IDCT module. The mode of operation may depend on whether the received video signal is in JPEG, MPEG, and/or H.263 format. The processing network may be configured into a DCT processing network configuration or an IDCT processing network configuration based on whether the received video signal is to be encoded or decoded respectively. The DCT/IDCT module may comprise a FIFO, an adder/subtractor, a multiplier/accumulator, a plurality of digital dividers, and a de-quantizer. The plurality of digital dividers may comprise a 12-bit divider and an 7-bit divider. The mode and configuration modifications may be dynamically performed during operation of the wireless handset.

Abstract: A system for implementing Incremental Redundancy (IR) operations in a wireless receiver includes a baseband processor, an equalizer, a system processor, a plurality of IR processing module registers, and an IR processing module. The baseband processor receives an analog signal and produces samples. The equalizer is operable to receive the samples, to equalize the samples, and to produce soft decision bits corresponding to the data block. The system processor receives the soft decision bits of the data block, configures the plurality of IR processing module registers, and initiates operations of the IR processing module. The IR processing module accesses the plurality of IR processing module registers, receives the soft decision bits of the data block, and performs IR operations on the soft decision bits of the data block in an attempt to correctly decode the data block.

Abstract: A system for implementing Incremental Redundancy (IR) operations in a wireless receiver includes a baseband processor, an equalizer, a system processor, a plurality of IR processing module registers, and an IR processing module. The baseband processor receives an analog signal and produces samples. The equalizer is operable to receive the samples, to equalize the samples, and to produce soft decision bits corresponding to the data block. The system processor receives the soft decision bits of the data block, configures the plurality of IR processing module registers, and initiates operations of the IR processing module. The IR processing module accesses the plurality of IR processing module registers, receives the soft decision bits of the data block, and performs IR operations on the soft decision bits of the data block in an attempt to correctly decode the data block.

Abstract: A recursive, single-wrong-turn (SWT) decoding method and Viterbi decoder which requires no additional circuitry or processing to keep track of a running list of the L best paths. If the most likely (ML) path fails frame quality metric tests, a search is made through a trellis using an existing survivor (trace back) information stored in a survivor (trace back) memory. An iteration in the recursive algorithm includes tracing back along the ML path to a particular stage, then deviating from the ML path and following the survivor information along that new deviant path, and finally checking the fully decoded frame to see if the frame quality metrics are acceptable for the frame. These same trace back steps can be performed for every stage in the trellis, deviating from a different stage on the ML path each time.

Abstract: The base station system includes a cancellation processor connected to a plurality of conventional signal processors. Under the control of a controller, the signal processors acquire user signals in signals received by the base station antennas. The controller controls the cancellation processor to perform cancellation operations with respect to the acquired user signals. The cancellation processor includes first-nth filter stages. Each filter stage operates in the same manner. A filter stage obtains, in parallel, the acquired user signals from signals supplied thereto by estimating symbols in the acquired user signals under the control of the controller. The cancellation processor also includes a cancellation stage associated with each filter stage. Each cancellation stage cancels, in parallel, the obtained user signals output from the associated filter stage from the signals received by the base station antennas.