Abstract: In one general aspect, a method can include configuring a first connector of a particular type included in a first multipurpose port located on a first side of a computing device to connect the computing device to a first peripheral device, transporting one or more of power, high-speed data, and display data between the computing device and the first peripheral device using the first multipurpose port, configuring a second connector of the particular type included in a second multipurpose port located on a second side of the computing device to connect the computing device to a second peripheral device, and transporting one or more of power, high-speed data, and display data between the computing device and the second peripheral device using the second multipurpose port.

Abstract: In one general aspect, a method can include determining an orientation of a plug inserted into a connector included in the computing device, providing a plurality of display data signals to a reordering switch included in the computing device, selecting, by the reordering switch and based on the determined orientation of the plug, a display data signal from the plurality of display data signals, providing the selected display data signal to at least one of a plurality of multiplexers, the plurality of multiplexers being orientated back-to-back, providing a data signal to the at least one of the plurality of multiplexers, enabling the at least one of the plurality of multiplexers, selecting the display data signal for output by the at least one of the plurality of multiplexers, and providing the selected display data signal to a contact included on the connector.

Abstract: A power brick includes a power module configured to convert AC to DC, an interface coupled to a computing device and configured to communicate with the computing device, and a controller. The controller is configured to receive a modified power setting and at least one modified error threshold value via the interface, control a modification of a power setting associated with the power module, and control a modification of a protection value of the power brick based on the at least one modified error threshold value.

Abstract: In one general aspect, a method can include obtaining, by a computing device, a lid accelerometer vector for a lid accelerometer included in a lid portion of the computing device, and obtaining, by the computing device, a base accelerometer vector for a base accelerometer included in a base portion of the computing device. The method can include calculating a value for a lid angle based on the lid accelerometer vector and the base accelerometer vector, and identifying an operating mode for the computing device based on the calculated value of the lid angle, the operating mode being one of a laptop mode and a tablet mode.

Abstract: In a general aspect, a circuit can include a printed circuit board having an opening defined therein and an electrical write line disposed on the circuit board. The electrical write line can be connected to a semiconductor memory device, and be configured to transmit a write voltage signal to the semiconductor memory device to write data therein in a write mode of the circuit. The circuit can also include an input voltage terminal disposed on the circuit board. The input voltage terminal can be configured to receive a write-protection voltage. The circuit can also include a reversible closing element that, when inserted in the opening in the circuit board, electrically connects the electrical write line and the input voltage terminal to pass the write- protection voltage to the electrical write line connected to the semiconductor memory device to reversibly enable a write-protect mode of the circuit.

Abstract: In one general aspect, a method can include determining an orientation of a plug inserted into a connector included in the computing device, providing a plurality of display data signals to a reordering switch included in the computing device, selecting, by the reordering switch and based on the determined orientation of the plug, a display data signal from the plurality of display data signals, providing the selected display data signal to at least one of a plurality of multiplexers, the plurality of multiplexers being orientated back-to-back, providing a data signal to the at least one of the plurality of multiplexers, enabling the at least one of the plurality of multiplexers, selecting the display data signal for output by the at least one of the plurality of multiplexers, and providing the selected display data signal to a contact included on the connector.

Abstract: In one general aspect, a method can include configuring a first connector of a particular type included in a first multipurpose port located on a first side of a computing device to connect the computing device to a first peripheral device, transporting one or more of power, high-speed data, and display data between the computing device and the first peripheral device using the first multipurpose port, configuring a second connector of the particular type included in a second multipurpose port located on a second side of the computing device to connect the computing device to a second peripheral device, and transporting one or more of power, high-speed data, and display data between the computing device and the second peripheral device using the second multipurpose port.

Abstract: In one general aspect, a method can include obtaining, by a computing device, a lid accelerometer vector for a lid accelerometer included in a lid portion of the computing device, and obtaining, by the computing device, a base accelerometer vector for a base accelerometer included in a base portion of the computing device. The method can include calculating a value for a lid angle based on the lid accelerometer vector and the base accelerometer vector, and identifying an operating mode for the computing device based on the calculated value of the lid angle, the operating mode being one of a laptop mode and a tablet mode.

Abstract: In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.

Abstract: An apparatus (e.g., a computer device) includes a power system. The power system includes a universal serial bus (USB) adapter communicatively coupled to a USB power source with a power bus, a first controller configured to increase a current associated with the USB power source, a second controller configured to determine a power utilization of the computer device, and a third controller configured to couple a battery to the power bus based on the determined power utilization such that a current associated with the USB power source does not exceed a threshold current rating of the USB power source. The apparatus includes a display configured to inform a user of the device of a power limitation of the USB power source based on the determined power utilization.

Abstract: In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.

Abstract: In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.

Abstract: In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

Abstract: In one embodiment, a system comprises at least a first node and a second node coupled to a network. The second node comprises a local memory and a direct memory access (DMA) controller coupled to the local memory. The first node is configured to transmit at least a first packet to the second node to access data in the local memory and at least one other packet that is not coded to access the local memory. The second node is configured to capture the packet from a data link layer of a protocol stack, and wherein the DMA controller is configured to perform one more transfers with the local memory to access the data specified by the first packet responsive to the first packet received from the data link layer. The second node is configured to process the other packet to a top of the protocol stack.

Abstract: In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.

Abstract: In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.

Abstract: In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

Abstract: In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.

Abstract: In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

Abstract: In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.