Patents by Inventor Mark D. Jacunski
Mark D. Jacunski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10535379Abstract: A latching current sensing amplifier circuit for memory arrays and a current sensing technique using the latching current sensing amplifier circuit are provided. The current sense-amplifier circuit includes a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as a cross-coupled pair for a latching operation.Type: GrantFiled: September 5, 2017Date of Patent: January 14, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Darren L. Anand, John A. Fifield, Eric D. Hunt-Schroeder, Mark D. Jacunski
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Patent number: 10429434Abstract: Disclosed are an on-chip reliability monitor and method. The monitor includes a test circuit with a test device, a reference circuit with a reference device, and a comparator circuit. The monitor periodically switches from operation in a stress mode, to operation in a test mode, and back. During each stress mode, the test device is subjected to stress conditions that emulate the operating conditions of an on-chip functional device while the reference device remains essentially unstressed. During each test mode, the comparator circuit compares a parameter of the test device to the same parameter of the reference device and outputs a status signal based on the difference between the parameters. When the status signal switches values, it is an indicator that the functional device has been subjected to a predetermined number of power-on-hours. Optionally, multiple monitors can be cascaded together to more accurately monitor stress-induced changes over time.Type: GrantFiled: February 23, 2018Date of Patent: October 1, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: John A. Fifield, Eric Hunt-Schroeder, Mark D. Jacunski
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Publication number: 20190265293Abstract: Disclosed are an on-chip reliability monitor and method. The monitor includes a test circuit with a test device, a reference circuit with a reference device, and a comparator circuit. The monitor periodically switches from operation in a stress mode, to operation in a test mode, and back. During each stress mode, the test device is subjected to stress conditions that emulate the operating conditions of an on-chip functional device while the reference device remains essentially unstressed. During each test mode, the comparator circuit compares a parameter of the test device to the same parameter of the reference device and outputs a status signal based on the difference between the parameters. When the status signal switches values, it is an indicator that the functional device has been subjected to a predetermined number of power-on-hours. Optionally, multiple monitors can be cascaded together to more accurately monitor stress-induced changes over time.Type: ApplicationFiled: February 23, 2018Publication date: August 29, 2019Inventors: John A. Fifield, Eric Hunt-Schroeder, Mark D. Jacunski
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Patent number: 10020047Abstract: Approaches for a write assist circuit are provided. The write assist circuit includes a boost capacitor with a first node coupled to a bitline through control logic and a second node connected to a field effect transistor (FET) diode stack, a plurality of boot enabled transistors which each contain a gate connected to a boost control signal, and a controlled current source coupled between a ground signal and the second node of the boost capacitor. In the write assist circuit, the boost capacitor has a discharge path which is controlled to provide a boost voltage which is invariant to a level of a power supply signal.Type: GrantFiled: March 21, 2016Date of Patent: July 10, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Eric D. Hunt-Schroeder, John A. Fifield, Mark D. Jacunski
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Publication number: 20170365302Abstract: A latching current sensing amplifier circuit for memory arrays and a current sensing technique using the latching current sensing amplifier circuit are provided. The current sense-amplifier circuit includes a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as a cross-coupled pair for a latching operation.Type: ApplicationFiled: September 5, 2017Publication date: December 21, 2017Inventors: Darren L. ANAND, John A. FIFIELD, Eric D. HUNT-SCHROEDER, Mark D. JACUNSKI
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Patent number: 9779783Abstract: A latching current sensing amplifier circuit for memory arrays and a current sensing technique using the latching current sensing amplifier circuit are provided. The current sense-amplifier circuit includes a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as a cross-coupled pair for a latching operation.Type: GrantFiled: June 19, 2015Date of Patent: October 3, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Darren L. Anand, John A. Fifield, Eric D. Hunt-Schroeder, Mark D. Jacunski
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Publication number: 20170270999Abstract: Approaches for a write assist circuit are provided. The write assist circuit includes a boost capacitor with a first node coupled to a bitline through control logic and a second node connected to a field effect transistor (FET) diode stack, a plurality of boot enabled transistors which each contain a gate connected to a boost control signal, and a controlled current source coupled between a ground signal and the second node of the boost capacitor. In the write assist circuit, the boost capacitor has a discharge path which is controlled to provide a boost voltage which is invariant to a level of a power supply signal.Type: ApplicationFiled: March 21, 2016Publication date: September 21, 2017Inventors: Eric D. HUNT-SCHROEDER, John A. FIFIELD, Mark D. JACUNSKI
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Publication number: 20160372164Abstract: A latching current sensing amplifier circuit for memory arrays and a current sensing technique using the latching current sensing amplifier circuit are provided. The current sense-amplifier circuit includes a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as a cross-coupled pair for a latching operation.Type: ApplicationFiled: June 19, 2015Publication date: December 22, 2016Inventors: Darren L. ANAND, John A. FIFIELD, Eric D. HUNT-SCHROEDER, Mark D. JACUNSKI
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Patent number: 9093175Abstract: Apparatus and methods for signal margin centering for single-ended eDRAM sense amplifier. A plurality of DRAM cells is connected to an input side of a multiplexer by a first bitline. A single-ended sense amplifier is connected to an output side of the multiplexer by a second bitline. The single-ended sense amplifier has a switch voltage. The second bitline is precharged to a selected voltage level. The multiplexer passes a signal voltage from a selected one of the plurality of DRAM cells to the second bitline. The selected voltage level is selected such that reception of the signal voltage of a first type adjusts a voltage of the second bitline in a first direction and reception of the signal voltage of a second type adjusts the voltage of the second bitline in a second direction opposite from the first direction, centering the signal voltage around the switch voltage.Type: GrantFiled: March 27, 2013Date of Patent: July 28, 2015Assignee: International Business Machines CorporationInventors: John E. Barth, Jr., John A. Fifield, Mark D. Jacunski
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Patent number: 8902679Abstract: Disclosed is a memory array structure, where a wordline driver selectively applies a high on-state voltage (VWLH) or a low off-state voltage (VWLL) to a wordline. VWLH has a slightly negative temperature coefficient so that it is regulated as high as the gate dielectric reliability limits allow, whereas VWLL has a substantially neutral temperature coefficient. To accomplish this, the wordline driver is coupled to one or more voltage regulation circuits. In one embodiment, the wordline driver is coupled to a single voltage regulation circuit, which incorporates a single voltage reference circuit having a single output stage that outputs multiple reference voltages. Also disclosed is a voltage reference circuit, which can be incorporated into the voltage regulation circuit of a memory array structure, as described, or, alternatively, into any other integrated circuit structure requiring voltages with different temperature coefficients. Also disclosed is a method of operating a memory array structure.Type: GrantFiled: June 27, 2012Date of Patent: December 2, 2014Assignee: International Business Machines CorporationInventors: John A. Fifield, Mark D. Jacunski
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Publication number: 20140293715Abstract: Apparatus and methods for signal margin centering for single-ended eDRAM sense amplifier. A plurality of DRAM cells is connected to an input side of a multiplexer by a first bitline. A single-ended sense amplifier is connected to an output side of the multiplexer by a second bitline. The single-ended sense amplifier has a switch voltage. The second bitline is precharged to a selected voltage level. The multiplexer passes a signal voltage from a selected one of the plurality of DRAM cells to the second bitline. The selected voltage level is selected such that reception of the signal voltage of a first type adjusts a voltage of the second bitline in a first direction and reception of the signal voltage of a second type adjusts the voltage of the second bitline in a second direction opposite from the first direction, centering the signal voltage around the switch voltage.Type: ApplicationFiled: March 27, 2013Publication date: October 2, 2014Applicant: International Business Machines CorporationInventors: JOHN E. BARTH, JR., John A. Fifield, Mark D. Jacunski
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Patent number: 8649239Abstract: Disclosed are embodiments of a multi-bank random access memory (RAM) structure that provides signal buffering at both the global and local connector level for improved performance. Specifically, inverters are incorporated into the global connector(s), which traverse groups of memory banks and which transmit signals (e.g., address signals, control signals, and/or data signals) from a memory controller, and also into alternating groups of local connectors, which connect nodes on the global connector(s) to corresponding groups of memory banks, such that any of the signals that are received by the memory banks from the memory controller via the global and local connectors are buffered by an even number of inverters and are thereby true signals. Signal buffering at both the global and local connector level results in relatively fast slews, short propagation delays, and low peak power consumption with minimal, if any, increase in area consumption.Type: GrantFiled: May 24, 2012Date of Patent: February 11, 2014Assignee: International Business Machines CorporationInventors: Darren L. Anand, John A. Fifield, Mark D. Jacunski, Matthew C. Lanahan
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Publication number: 20140003164Abstract: Disclosed is a memory array structure, where a wordline driver selectively applies a high on-state voltage (VWLH) or a low off-state voltage (VWLL) to a wordline. VWLH has a slightly negative temperature coefficient so that it is regulated as high as the gate dielectric reliability limits allow, whereas VWLL has a substantially neutral temperature coefficient. To accomplish this, the wordline driver is coupled to one or more voltage regulation circuits. In one embodiment, the wordline driver is coupled to a single voltage regulation circuit, which incorporates a single voltage reference circuit having a single output stage that outputs multiple reference voltages. Also disclosed is a voltage reference circuit, which can be incorporated into the voltage regulation circuit of a memory array structure, as described, or, alternatively, into any other integrated circuit structure requiring voltages with different temperature coefficients. Also disclosed is a method of operating a memory array structure.Type: ApplicationFiled: June 27, 2012Publication date: January 2, 2014Applicant: International Business Machines CorporationInventors: John A. Fifield, Mark D. Jacunski
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Publication number: 20130315022Abstract: Disclosed are embodiments of a multi-bank random access memory (RAM) structure that provides signal buffering at both the global and local connector level for improved performance. Specifically, inverters are incorporated into the global connector(s), which traverse groups of memory banks and which transmit signals (e.g., address signals, control signals, and/or data signals) from a memory controller, and also into alternating groups of local connectors, which connect nodes on the global connector(s) to corresponding groups of memory banks, such that any of the signals that are received by the memory banks from the memory controller via the global and local connectors are buffered by an even number of inverters and are thereby true signals. Signal buffering at both the global and local connector level results in relatively fast slews, short propagation delays, and low peak power consumption with minimal, if any, increase in area consumption.Type: ApplicationFiled: May 24, 2012Publication date: November 28, 2013Applicant: International Business Machines CorporationInventors: Darren L. Anand, John A. Fifield, Mark D. Jacunski, Matthew C. Lanahan
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Publication number: 20120036315Abstract: A memory circuit comprises a memory array including a plurality of memory cells, multiple word lines, and at least one bit line. Each of the memory cells is coupled to a unique pair of a bit line and a word line for selectively accessing the memory cells. The memory circuit further includes at least one control circuit coupled to the word lines and operative to selectively change an operation of the memory array between a first data storage mode and at least a second data storage mode as a function of at least one control signal supplied to the control circuit. In the first data storage mode, each of the memory cells is allocated to a corresponding stored logic bit, and in the second data storage mode, at least two memory cells are allocated to a corresponding stored logic bit.Type: ApplicationFiled: August 9, 2010Publication date: February 9, 2012Applicant: International Business Machines CorporationInventors: William R. Reohr, Darren L. Anand, Mark D. Jacunski
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Patent number: 7221601Abstract: A SDRAM. The SDRAM including: at least one bank of DRAM cells; the SDRAM operable to a first specification defined by a first clock frequency, a first write recovery time and a first time interval for precharge to row address strobe; and means for programming the SDRAM operable to a second specification defined by a second clock frequency, a second write recovery time and a second time interval for precharge to row address strobe.Type: GrantFiled: February 28, 2006Date of Patent: May 22, 2007Assignee: International Business Machines CorporationInventors: Mark D. Jacunski, Alan D. Norris, Samuel K. Weinstein
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Patent number: 7194670Abstract: Disclosed is a flexible command multiplication scheme for the built-in-self test (BIST) of a high-speed embedded memory array that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A stand-alone BIST logic controller operates at a lower frequency and communicates with a command multiplier using a low-speed BIST instruction seed set. The command multiplier uses offset or directive registers to drive a logic unit or ALU to generate ānā sets of CAD information which are then time-multiplexed to the embedded memory at a speed ānā times faster than the BIST operating speed.Type: GrantFiled: February 13, 2004Date of Patent: March 20, 2007Assignee: International Business Machines Corp.Inventors: Jonathan R. Fales, Gregory J. Fredeman, Kevin W. Gorman, Mark D. Jacunski, Toshiaki Kirihata, Alan D. Norris, Paul C. Parries, Matthew R. Wordeman
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Patent number: 7085180Abstract: A method for allocating redundancies during a multi-bank operation in a memory device which includes two or more redundancy domains is described. The method includes steps of enabling a pass/fail bit detection to activate a given bank. The pass/fail bit detection is prompted only for a selected domain and is disabled when it addresses other domains. By altering the domain selection, it is possible to enable a redundancy allocation for any domain regardless of the multi-bank operation. The method may preferably be realized by using a dynamic exclusive-OR logic with true and complement expected data pairs. When combined with simple pointer logic, the selection of domains may be generated internally, simplifying the built in self-test and other test control protocols, while at the same time tracking those that fail.Type: GrantFiled: February 12, 2004Date of Patent: August 1, 2006Assignee: International Business Machines CorporationInventors: Gregory J. Fredeman, Mark D. Jacunski, Toshiaki Kirihata, Matthew R. Wordeman
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Patent number: 7068564Abstract: A SDRAM mid a tinier lockout circuit. The SDRAM including: at least one bank of DRAM cells; the SDRAM operable to a first specification defined by a first clock frequency, a first write recovery time and a first time interval for precharge to row address strobe; and a circuit for programming the SDRAM operable to a second specification defined by a second clock frequency, a second write recovery time and a second time interval for precharge to row address strobe.Type: GrantFiled: June 29, 2003Date of Patent: June 27, 2006Assignee: International Business Machines CorporationInventors: Mark D Jacunski, Alan D Norris, Samuel K Weinstein
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Publication number: 20040264289Abstract: A SDRAM including: at least one bank of DRAM cells; the SDRAM operable to a first specification defined by a first clock frequency, a first write recovery time and a first time interval for precharge to row address strobe; and means for programming the SDRAM operable to a second specification defined by a second clock frequency, a second write recovery time and a second time interval for precharge to row address strobe.Type: ApplicationFiled: June 29, 2003Publication date: December 30, 2004Applicant: International Business Machines CorporationInventors: Mark D Jacunski, Alan D Norris, Samuel K Weinstein