Patents by Inventor Mark D. Kellam

Mark D. Kellam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250182817
    Abstract: Technologies for multi-port memory devices with built-in configurable logic blocks are described. A dynamic random access memory (DRAM) device includes one or more stacks of memory dies, and a base die having at least two ports. Each of the at least two ports includes one or more sub-ports. The DRAM device includes a configurable logic block on the base die to perform an operation on data from the one or more sub-ports or the one or more stacks of memory dies.
    Type: Application
    Filed: November 11, 2024
    Publication date: June 5, 2025
    Inventors: Dongyun Lee, Mark D. Kellam
  • Patent number: 12292601
    Abstract: Command/address and timing information is distributed to buffer integrated circuits on a module using multiple wavelengths of light modulated with the same information. Each individual wavelength of modulated light carrying command/address information is received by a corresponding single buffer device that deserializes the command/address information and communicates it electrically to memory devices(s). Likewise, each individual wavelength of modulated light carrying timing/synchronization/clock information is received by a corresponding single buffer device and used to synchronize accesses to the memory device(s). Thus, multiple buffer integrated circuits on a module each receive information from the CPU using different wavelengths of light transmitted on the same waveguide.
    Type: Grant
    Filed: October 10, 2022
    Date of Patent: May 6, 2025
    Assignee: Rambus inc.
    Inventors: Mark D. Kellam, Dongyun Lee, Thomas Vogelsang, Steven C. Woo
  • Patent number: 12237255
    Abstract: The embodiments are directed to technologies for variable pitch vertical interconnect design for scalable escape routing in semiconductor devices. One semiconductor device includes a circuit die, and an array of circuit die interconnects located on the circuit die. The array includes a first triangular octant of interconnects that are organized in rows and columns, each column incrementing its number of interconnects from a first side of the first triangular octant to a second side of the first triangular octant. A pitch size between the columns increases in a first repeating pattern from the first side to the second side.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: February 25, 2025
    Assignee: Rambus Inc.
    Inventors: Mark D. Kellam, John Eric Linstadt
  • Publication number: 20250061935
    Abstract: An interposer interconnecting a first integrated circuit and a second integrated circuit includes active circuitry. The “active” interposer converts high-speed signals into lower-speed, but more parallelized, signals for transmission across the active interposer. The parallelized signals may be buffered or amplified at intervals while crossing the active interposer. The high-speed to low-speed, and back, conversions may be performed by an appropriately configured and controlled multiplexer/demultiplexer circuitry The supply voltages for some interposer circuits may be different than the supply voltages for the interfaces with the first and second integrated circuit. One or more of the interconnected integrated circuits may supply, and/or calibrate the supply voltages for the interposer circuitry. Timing signals provided by one or more of the interconnected integrated circuits may also be calibrated using circuitry on the active interposer.
    Type: Application
    Filed: August 7, 2024
    Publication date: February 20, 2025
    Inventors: Dongyun LEE, Mark D. KELLAM, Joohee KIM
  • Publication number: 20240395327
    Abstract: Control logic within a memory control component outputs first and second memory read commands to a memory module at respective times, the memory module having memory components disposed thereon. Interface circuitry within the memory control component receives first read data concurrently from a first plurality of the memory components via a first plurality of data paths, respectively, in response to the first memory read command, and receives second read data concurrently from a second plurality of the memory components via a second plurality of data paths, respectively, in response to the second memory read command, the first plurality of the memory components including at least one memory component not included in the second plurality of the memory components and vice-versa.
    Type: Application
    Filed: April 25, 2024
    Publication date: November 28, 2024
    Inventors: Gary B. Bronner, Brent Steven Haukness, Mark A. Horowitz, Mark D. Kellam, Fariborz Assaderaghi
  • Patent number: 12149289
    Abstract: A photonic communication system in which a host communicates bidirectionally with a target via a single optical fiber using light of the same wavelength and from the same light source. Signals flowing in opposite directions are discriminated based on polarity. Using the same fiber and light source in both directions reduces cost, complexity, and power consumption.
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: November 19, 2024
    Assignee: Rambus Inc.
    Inventors: Mark D. Kellam, Carl W. Werner
  • Patent number: 12147351
    Abstract: Memory pages are background-relocated from a low-latency local operating memory of a server computer to a higher-latency memory installation that enables high-resolution access monitoring and thus access-demand differentiation among the relocated memory pages. Higher access-demand memory pages are background-restored to the low-latency operating memory, while lower access-demand pages are maintained in the higher latency memory installation and yet-lower access-demand pages are optionally moved to yet higher-latency memory installation.
    Type: Grant
    Filed: April 25, 2023
    Date of Patent: November 19, 2024
    Assignee: Rambus Inc.
    Inventors: Evan Lawrence Erickson, Christopher Haywood, Mark D. Kellam
  • Patent number: 12002513
    Abstract: Control logic within a memory control component outputs first and second memory read commands to a memory module at respective times, the memory module having memory components disposed thereon. Interface circuitry within the memory control component receives first read data concurrently from a first plurality of the memory components via a first plurality of data paths, respectively, in response to the first memory read command, and receives second read data concurrently from a second plurality of the memory components via a second plurality of data paths, respectively, in response to the second memory read command, the first plurality of the memory components including at least one memory component not included in the second plurality of the memory components and vice-versa.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: June 4, 2024
    Assignee: Rambus Inc.
    Inventors: Gary B. Bronner, Brent Steven Haukness, Mark A. Horowitz, Mark D. Kellam, Fariborz Assaderaghi
  • Publication number: 20230410898
    Abstract: A flash memory cell of a flash memory device is illuminated with light during programming and/or erasing. The wavelength of the light is selected such that the photons impinging on the flash memory cell have an energy that approaches the barrier height (conduction band offset) of the tunnel insulator. Illuminating the flash memory cell during programming/erase increases the tunneling current through the tunnel insulator by way of the photon assisted tunneling (PAT) effect.
    Type: Application
    Filed: October 5, 2021
    Publication date: December 21, 2023
    Inventor: Mark D. KELLAM
  • Publication number: 20230333989
    Abstract: Memory pages are background-relocated from a low-latency local operating memory of a server computer to a higher-latency memory installation that enables high-resolution access monitoring and thus access-demand differentiation among the relocated memory pages. Higher access-demand memory pages are background-restored to the low-latency operating memory, while lower access-demand pages are maintained in the higher latency memory installation and yet-lower access-demand pages are optionally moved to yet higher-latency memory installation.
    Type: Application
    Filed: April 25, 2023
    Publication date: October 19, 2023
    Inventors: Evan Lawrence Erickson, Christopher Haywood, Mark D. Kellam
  • Patent number: 11663138
    Abstract: Memory pages are background-relocated from a low-latency local operating memory of a server computer to a higher-latency memory installation that enables high-resolution access monitoring and thus access-demand differentiation among the relocated memory pages. Higher access-demand memory pages are background-restored to the low-latency operating memory, while lower access-demand pages are maintained in the higher latency memory installation and yet-lower access-demand pages are optionally moved to yet higher-latency memory installation.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: May 30, 2023
    Assignee: Rambus Inc.
    Inventors: Evan Lawrence Erickson, Christopher Haywood, Mark D. Kellam
  • Publication number: 20230139848
    Abstract: A photonic communication system in which a host communicates bidirectionally with a target via a single optical fiber using light of the same wavelength and from the same light source. Signals flowing in opposite directions are discriminated based on polarity. Using the same fiber and light source in both directions reduces cost, complexity, and power consumption.
    Type: Application
    Filed: October 17, 2022
    Publication date: May 4, 2023
    Inventors: Mark D. Kellam, Carl W. Werner
  • Publication number: 20230125262
    Abstract: Command/address and timing information is distributed to buffer integrated circuits on a module using multiple wavelengths of light modulated with the same information. Each individual wavelength of modulated light carrying command/address information is received by a corresponding single buffer device that deserializes the command/address information and communicates it electrically to memory devices(s). Likewise, each individual wavelength of modulated light carrying timing/synchronization/clock information is received by a corresponding single buffer device and used to synchronize accesses to the memory device(s). Thus, multiple buffer integrated circuits on a module each receive information from the CPU using different wavelengths of light transmitted on the same waveguide.
    Type: Application
    Filed: October 10, 2022
    Publication date: April 27, 2023
    Inventors: Mark D. KELLAM, Dongyun LEE, Thomas VOGELSANG, Steven C. WOO
  • Publication number: 20230008889
    Abstract: Multidrop optical connections are used for an optical memory module. Multiple buffer integrated circuits on a module each receive information from the host system using different wavelengths of light transmitted on the same waveguide. Multiple buffer integrated circuits each transmit information back to the CPU using different wavelengths of light transmitted on another waveguide. Wavelength resonant ring couplers disposed on the buffer integrated circuits are used to separate the wavelength being received by a particular buffer integrated circuit from the wavelengths of light destined for other buffer integrated circuits on the same waveguide. Wavelength resonant ring modulators also disposed on the buffer integrated circuits modulate specific wavelengths of light unique to each buffer integrated circuit to transmit information to the CPU.
    Type: Application
    Filed: June 28, 2022
    Publication date: January 12, 2023
    Inventors: Thomas VOGELSANG, Mark D. KELLAM
  • Publication number: 20220269436
    Abstract: An integrated circuit that includes a set of one or more logic layers that are, when the integrated circuit is stacked in an assembly with the set of stacked memory devices, electrically coupled to a set of stacked memory devices. The set of one or more logic layers include a coupled chain of processing elements. The processing elements in the coupled chain may independently compute partial results as functions of data received, store partial results, and pass partial results directly to a next processing element in the coupled chain of processing elements. The processing elements in the chains may include interfaces that allow direct access to memory banks on one or more DRAMs in the stack. These interfaces may access DRAM memory banks via TSVs that are not used for global I/O. These interfaces allow the processing elements to have more direct access to the data in the DRAM.
    Type: Application
    Filed: July 6, 2020
    Publication date: August 25, 2022
    Inventors: Mark D. KELLAM, Steven C. WOO, Thomas VOGELSANG, John Eric LINSTADT
  • Publication number: 20220238159
    Abstract: Control logic within a memory control component outputs first and second memory read commands to a memory module at respective times, the memory module having memory components disposed thereon. Interface circuitry within the memory control component receives first read data concurrently from a first plurality of the memory components via a first plurality of data paths, respectively, in response to the first memory read command, and receives second read data concurrently from a second plurality of the memory components via a second plurality of data paths, respectively, in response to the second memory read command, the first plurality of the memory components including at least one memory component not included in the second plurality of the memory components and vice-versa.
    Type: Application
    Filed: January 3, 2022
    Publication date: July 28, 2022
    Inventors: Gary B. Bronner, Brent Steven Haukness, Mark A. Horowitz, Mark D. Kellam, Fariborz Assaderaghi
  • Publication number: 20220179799
    Abstract: Memory pages are background-relocated from a low-latency local operating memory of a server computer to a higher-latency memory installation that enables high-resolution access monitoring and thus access-demand differentiation among the relocated memory pages. Higher access-demand memory pages are background-restored to the low-latency operating memory, while lower access-demand pages are maintained in the higher latency memory installation and yet-lower access-demand pages are optionally moved to yet higher-latency memory installation.
    Type: Application
    Filed: December 6, 2021
    Publication date: June 9, 2022
    Inventors: Evan Lawrence Erickson, Christopher Haywood, Mark D. Kellam
  • Publication number: 20220130745
    Abstract: The embodiments are directed to technologies for variable pitch vertical interconnect design for scalable escape routing in semiconductor devices. One semiconductor device includes a circuit die, and an array of circuit die interconnects located on the circuit die. The array includes a first triangular octant of interconnects that are organized in rows and columns, each column incrementing its number of interconnects from a first side of the first triangular octant to a second side of the first triangular octant. A pitch size between the columns increases in a first repeating pattern from the first side to the second side.
    Type: Application
    Filed: October 12, 2021
    Publication date: April 28, 2022
    Inventors: Mark D. Kellam, John Eric Linstadt
  • Patent number: 11244727
    Abstract: Control logic within a memory control component outputs first and second memory read commands to a memory module at respective times, the memory module having memory components disposed thereon. Interface circuitry within the memory control component receives first read data concurrently from a first plurality of the memory components via a first plurality of data paths, respectively, in response to the first memory read command, and receives second read data concurrently from a second plurality of the memory components via a second plurality of data paths, respectively, in response to the second memory read command, the first plurality of the memory components including at least one memory component not included in the second plurality of the memory components and vice-versa.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: February 8, 2022
    Assignee: Rambus Inc.
    Inventors: Gary B. Bronner, Brent S. Haukness, Mark A. Horowitz, Mark D. Kellam, Fariborz Assaderaghi
  • Patent number: 10614883
    Abstract: A resistance memory includes a resistance memory cell having a resistance memory element and a two-terminal access device in series. The two-terminal access device affects the current-voltage characteristic of the resistance memory cell. The resistance memory additionally includes a circuit to apply across the resistance memory cell a set pulse having a set polarity to set the resistance memory cell to a low-resistance state that is retained after application of the set pulse, a reset pulse having a reset polarity, opposite to the set polarity, to reset the resistance memory cell to a high-resistance state that is retained after application of the reset pulse, and a read pulse of the reset polarity and smaller in magnitude than the reset pulse to determine the resistance state of the resistance memory cell without changing the resistance state of the resistance memory cell.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: April 7, 2020
    Assignee: Hefei Reliance Memory Limited
    Inventors: Mark D. Kellam, Gary Bela Bronner