Abstract: An input/output buffer including a bidirectional node, an output stage, an input stage, and a control circuit. The output stage has a first n-channel transistor coupled between the bidirectional node and a voltage supply node for pulling-up the bidirectional node, and first and second p-channel transistors coupled between the bidirectional node and the voltage supply node for pulling-up the bidirectional node. The input stage has a first inverter stage coupled between the bidirectional node and a first intermediate node and a second inverter stage coupled between the bidirectional node and a second intermediate node. The input stage also has a second n-channel transistor coupled between the first intermediate node and a ground node and a third n-channel transistor coupled between the second intermediate node and the ground node. The control circuit is coupled to the output stage and to the input stage and enables the output stage when in an output mode and disables the output stage when in an input mode.