Abstract: A structure includes an electrical device, and an active contact landed on a portion of the electrical device. The active contact includes a first body of a first material. A thermal dissipation pillar is adjacent the active contact and unlanded on but over the portion of the electrical device. The thermal dissipation pillar includes a second body of a second material having a higher thermal conductivity than the first material. The thermal dissipation pillar may be in thermal communication with a wire in a dielectric layer over the active contact and the thermal dissipation pillar. The electrical device can be any integrated circuit device that generates heat.

Abstract: The present disclosure relates to a structure which includes at least one gate structure over semiconductor material, the at least one gate structure comprising an active layer, a gate metal extending from the active layer and a sidewall spacer on sidewalls of the gate metal, and a field plate aligned with the at least one gate structure and isolated from the gate metal by the sidewall spacer.

Abstract: A structure includes a cavity in a semiconductor substrate; a field effect transistor positioned over the cavity; an opening in the semiconductor substrate extending to the cavity; and a layer of insulating material filling the opening and forming an insulating material window to the cavity.

Abstract: The disclosure relates to a PIC structure including a photonic component on a semiconductor substrate. Each of a plurality of optical guard elements are composed of a light absorbing material and are in proximity to the photonic component. The optical guard elements may mimic an outer periphery of at least a portion of the photonic component. The optical guard elements may include at least one of: a germanium body positioned at least partially in a silicon element, a silicon body having a high dopant concentration, and a polysilicon body having a high dopant concentration over the silicon body.

Abstract: A structure includes a lab-on-chip (LOC) sensor and frontside port and cavity features for conveying a flowable sample (fluid or gas) to a sensing element of the sensor. The cavity is confined within middle of the line (MOL) dielectric layer(s). Alternatively, the cavity includes a lower section within MOL dielectric layer(s), an upper section within back end of the line (BEOL) dielectric layer(s) in the first metal (M1) level, a divider between the sections, and a duct linking the sections. Alternatively, the cavity includes a lower portion within MOL dielectric layer(s) and an upper portion continuous with the lower portion and within BEOL dielectric layer(s) in the M1 level. Optionally, the cavity is separated from the sensing element by an additional dielectric layer and/or at least partially lined with a dielectric liner. The port extends from the top of the BEOL dielectric layers down to the cavity.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The structure includes: a gate structure comprising a horizontal portion and a substantially vertical stem portion; and an air gap surrounding the substantially vertical stem portion and having a curved surface under the horizontal portion.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a patterned buried porous layer of semiconductor material and a device over the patterned buried porous layer, and methods of manufacture. The structure includes: a semiconductor substrate includes a patterned buried porous layer within the semiconductor substrate; a semiconductor compound material over the semiconductor substrate and the patterned buried porous layer; and at least one device on the semiconductor compound material. The non-patterned portions of the semiconductor substrate provide a thermal pathway within the semiconductor substrate.

Abstract: Disclosed is a semiconductor structure with a photodiode including: a well region with a first-type conductivity in a substrate, a trench in the well region, and multiple conformal semiconductor layers in the trench. The semiconductor layers include a first semiconductor layer, which is, for example, an intrinsic semiconductor layer and lines the trench, and a second semiconductor layer, which has a second-type conductivity and which is on the first semiconductor layer within (but not filling) the trench and which also extends outside the trench onto a dielectric layer. An additional dielectric layer extends over and caps a cavity that is at least partially within the trench such that surfaces of the second semiconductor layer are exposed within the cavity. Fluid inlet/outlet ports extend to the cavity and contacts extend to the well region and to the second semiconductor layer. Also disclosed are methods for forming and using the semiconductor structure.

Abstract: Disclosed is a semiconductor structure including a monocrystalline silicon layer having a first surface and a second surface opposite the first surface. A cavity extends into the first semiconductor layer at the second surface. The structure also includes a polycrystalline silicon layer adjacent to the second surface and extending over the cavity. At least one opening extends through the second semiconductor layer to the cavity.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar junction transistor and methods of manufacture. The structure includes: a collector region; a base region adjacent to the collector region; an emitter region adjacent to the base region; contacts having a first material connecting to the collector region and the base region; and at least one contact having a second material connecting to the emitter region.

Abstract: Disclosed is a semiconductor structure including a device (e.g., a field effect transistor (FET), a biosensor FET (bioFET) or an ion-sensitive FET (ISFET)) with a fluid-based gate. The structure includes a substrate, an intermediate layer on the substrate, and a semiconductor layer on the intermediate layer. The device includes, within the semiconductor layer, a source region, a drain region, and a channel region between the source and drain regions. The structure includes, for the fluid-base gate, a cavity within the intermediate layer below the channel region and lined with a dielectric liner. Optionally, the exposed surface of the dielectric liner within the cavity is functionalized. Additional dielectric layers are stacked on the semiconductor layer and at least one port extends essentially vertically through the dielectric layers, the semiconductor layer and the dielectric liner to the cavity so as to allow fluid for the fluid-based gate to flow into the cavity.

Abstract: A semiconductor structure includes a semiconductor device (e.g., an e-fuse or photonic device) and a metallic heating element adjacent thereto. The heating element has a lower portion within a middle of the line (MOL) dielectric layer adjacent to the semiconductor device and an upper portion with a tapered top end that extends into a back end of the line (BEOL) dielectric layer. A method of forming the semiconductor structure includes forming a cavity such that it has both a lower section, which extends from a top surface of a MOL dielectric layer downward toward a semiconductor device, and an upper section, which extends from the top surface of the MOL dielectric layer upward and which is capped by an area of a BEOL dielectric layer having a concave bottom surface. A metallic fill material can then be deposited into the cavity (e.g., through via openings) to form the heating element.

Abstract: Disclosed are a transistor and a method for forming the transistor. The method includes concurrently forming gate and source/drain openings through an uppermost layer (i.e., a dielectric layer) in a stack of layers. The method can further include: depositing and patterning gate conductor material so that a first gate section is in the gate opening and a second gate section is above the gate opening and so that the source/drain openings are exposed; extending the depth of the source/drain openings; and depositing and patterning source/drain conductor material so that a first source/drain section is in each source/drain opening and a second source/drain section is above each source/drain opening. Alternatively, the method can include: forming a plug in the gate opening and sidewall spacers in the source/drain openings; extending the depth of source/drain openings; depositing and patterning the source/drain conductor material; and subsequently depositing and patterning the gate conductor material.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to switches in a bulk substrate and methods of manufacture. The structure includes: at least one active device having a channel region of a first semiconductor material; a single air gap under the channel region of the at least one active device; and a second semiconductor material being coplanar with and laterally bounding at least one side of the single air gap, the second semiconductor material being different material than the first semiconductor material.

Abstract: A structure includes an electrical device, and an active contact landed on a portion of the electrical device. The active contact includes a first body of a first material. A thermal dissipation pillar is adjacent the active contact and unlanded on but over the portion of the electrical device. The thermal dissipation pillar includes a second body of a second material having a higher thermal conductivity than the first material. The thermal dissipation pillar may be in thermal communication with a wire in a dielectric layer over the active contact and the thermal dissipation pillar. The electrical device can be any integrated circuit device that generates heat.

Abstract: Disclosed are a transistor and a method for forming the transistor. The method includes concurrently forming gate and source/drain openings through an uppermost layer (i.e., a dielectric layer) in a stack of layers. The method can further include: depositing and patterning gate conductor material so that a first gate section is in the gate opening and a second gate section is above the gate opening and so that the source/drain openings are exposed; extending the depth of the source/drain openings; and depositing and patterning source/drain conductor material so that a first source/drain section is in each source/drain opening and a second source/drain section is above each source/drain opening. Alternatively, the method can include: forming a plug in the gate opening and sidewall spacers in the source/drain openings; extending the depth of source/drain openings; depositing and patterning the source/drain conductor material; and subsequently depositing and patterning the gate conductor material.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a semiconductor device with a dual isolation structure and methods of manufacture. The structure includes: a dual isolation structure including semiconductor material; and an active device region including a channel material and a gate metal material over the channel material. The channel material is between the dual isolation structure and the gate metal material includes a bottom surface not extending beyond a sidewall of the dual isolation structure.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and/or PIN diode structures and methods of manufacture. The structure includes: a spiral fin structure comprising semiconductor substrate material and dielectric material; a photosensitive semiconductor material over sidewalls and a top surface of the spiral fin structure, the photosensitive semiconductor material positioned to capture laterally emitted incident light; a doped semiconductor material above the photosensitive semiconductor material; and contacts electrically contacting the semiconductor substrate material and the doped semiconductor material from a top surface thereof.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to switches in a bulk substrate and methods of manufacture. The structure includes: at least one active device having a channel region of a first semiconductor material; a single air gap under the channel region of the at least one active device; and a second semiconductor material being coplanar with and laterally bounding at least one side of the single air gap, the second semiconductor material being different material than the first semiconductor material.

Abstract: A structure includes a semiconductor-on-insulator (SOI) substrate including a semiconductor substrate, a buried insulator layer over the semiconductor substrate, and an SOI layer over the buried insulator layer. At least one polycrystalline active region fill shape is in the SOI layer. A polycrystalline isolation region may be in the semiconductor substrate under the buried insulator layer. The at least one polycrystalline active region fill shape is laterally aligned over the polycrystalline isolation region, where provided. Where provided, the polycrystalline isolation region may extend to different depths in the semiconductor substrate.