Abstract: The present disclosure generally relates to data storage devices, such as solid state drives. The data storage device includes a controller that includes a compression engine. The controller receives a ZNS append command to write data to a media, such as a non-volatile memory. The compression engine compresses data from a first number of logical blocks to second number of logical blocks. The compressed data is programmed to the media. The compressed data has a media logical block address and a host logical block address, where the media logical block address is the actual LBA where the ZNS append places the data on the media and the host logical block address is the location of the data stored on the media from the host's point of view. The host generates an index of the location of the stored data and the controller programs the index to the relevant location in the media.

Abstract: The present disclosure generally relates to data storage devices, such as solid state drives. The data storage device includes a controller that includes a compression engine. The controller receives a ZNS append command to write data to a media, such as a non-volatile memory. The compression engine compresses data from a first number of logical blocks to second number of logical blocks. The compressed data is programmed to the media. The compressed data has a media logical block address and a host logical block address, where the media logical block address is the actual LBA where the ZNS append places the data on the media and the host logical block address is the location of the data stored on the media from the host's point of view. The host generates an index of the location of the stored data and the controller programs the index to the relevant location in the media.

Abstract: The present disclosure generally relates to solid state storage device and techniques for conserving storage capacity associated therewith. Several embodiments are presented, including a data storage device, data storage controller, and methods for using the same are provided in the subject disclosure. A data storage device includes: a plurality of memory devices, a controller coupled to the plurality of memory devices and configured to program data to and read data from the plurality of memory devices, a memory including a logical-to-physical address translation map configured to enable the controller to determine a physical location of stored data in the plurality of memory devices, where the logical-to-physical address translation map contains at least one entry that merges at least two addresses that map, respectively, to at least two physical locations in the plurality of memory devices, where the controller is configured to encode each merged entry with an error-correcting code.

Abstract: The present disclosure generally relates to solid state storage device and techniques for conserving storage capacity associated therewith. Several embodiments are presented, including a data storage device, data storage controller, and methods for using the same are provided in the subject disclosure. A data storage device includes: a plurality of memory devices, a controller coupled to the plurality of memory devices and configured to program data to and read data from the plurality of memory devices, a memory including a logical-to-physical address translation map configured to enable the controller to determine a physical location of stored data in the plurality of memory devices, where the logical-to-physical address translation map contains at least one entry that merges at least two addresses that map, respectively, to at least two physical locations in the plurality of memory devices, where the controller is configured to encode each merged entry with an error-correcting code.

Abstract: A transaction processor pipeline architecture and associated apparatus for processing multiple queued transaction requests incorporates multiple processing elements working in parallel. Each processing element is configured to perform a specific function within the transaction processor system. Certain processing elements are assigned as function controllers, which are assigned to process specific transaction request subtask categories and may be augmented with dedicated hardware to accelerate certain subtask functions. Other processing elements are configured as list managers, which are optimized for managing data structure operations in memory. The processing elements are connected by a cross-point interconnect. The transaction processor system is configurable and scalable based on application needs.

Abstract: A transaction processor pipeline architecture and associated apparatus for processing multiple queued transaction requests incorporates multiple processing elements working in parallel. Each processing element is configured to perform a specific function within the transaction processor system. Certain processing elements are assigned as function controllers, which are assigned to process specific transaction request subtask categories and may be augmented with dedicated hardware to accelerate certain subtask functions. Other processing elements are configured as list managers, which are optimized for managing data structure operations in memory. The processing elements are connected by a cross-point interconnect. The transaction processor system is configurable and scalable based on application needs.

Abstract: A system for processing a plurality of tasks is disclosed. Each task has a plurality of component subtasks. The system may process N tasks and each task includes a first subtask, and a second subtask. The system for processing the plurality of tasks comprises a scalable transaction processing pipeline (STPP). The STPP comprises a plurality of processing elements, including at least a first processing element and a second processing element, the first processing element is adapted to process the first subtask of each task. The second processing element is adapted to process the second subtask of each task. Each successive processing element is adapted to process a corresponding subtask or subtasks of each task. The first processing element processes the first subtask of each task. When the first processing element finishes the processing of the first subtask, the second processing element processes the second subtask of each task.