Abstract: Aspects of charger detection and optimization prior to host control are described herein. In various embodiments, a condition of whether reverse current is present on a system bus is detected. When the condition for reverse current is present, reverse current is sunk by one or more of various reverse current sink circuits. By relying upon one or more of the reverse current sink circuits, for safety, to address or mitigate the condition for reverse current, a detector may be able to identify or distinguish among several different types of charger or charging ports coupled to a system bus allowing a charger to be selected optimally. Further, an indicator of the type of charger or charging port coupled to the system bus is communicated over a single pin interface, for backwards compatibility with circuits capable of identifying between only two different types of chargers.

Abstract: Aspects of dynamic power profiling are described herein. In various embodiments, a current sense operating mode is set for a current sense circuit, and the current sense circuit is enabled for operation. The current sense circuit senses an amount of current supplied by at least one of a plurality of power rails based on the current sense operating mode. The current sense circuit also accumulates and stores a value of the amount of current over a period of time. In certain aspects, a system controller averages the value of the amount of current based on the period of time. The current sense circuit may be configured to operate in various modes of operation including single or scan rail modes of operation, and the average of the value of the amount of current may be evaluated based on the modes of operation of the current sense circuit and/or the system.

Abstract: Aspects of dynamic power profiling are described herein. In various embodiments, a current sense operating mode is set for a current sense circuit, and the current sense circuit is enabled for operation. The current sense circuit senses an amount of current supplied by at least one of a plurality of power rails based on the current sense operating mode. The current sense circuit also accumulates and stores a value of the amount of current over a period of time. In certain aspects, a system controller averages the value of the amount of current based on the period of time. The current sense circuit may be configured to operate in various modes of operation including single or scan rail modes of operation, and the average of the value of the amount of current may be evaluated based on the modes of operation of the current sense circuit and/or the system.

Abstract: Aspects of charger detection and optimization prior to host control are described herein. In various embodiments, a condition of whether reverse current is present on a system bus is detected. When the condition for reverse current is present, reverse current is sunk by one or more of various reverse current sink circuits. By relying upon one or more of the reverse current sink circuits, for safety, to address or mitigate the condition for reverse current, a detector may be able to identify or distinguish among several different types of charger or charging ports coupled to a system bus allowing a charger to be selected optimally. Further, an indicator of the type of charger or charging port coupled to the system bus is communicated over a single pin interface, for backwards compatibility with circuits capable of identifying between only two different types of chargers.

Abstract: Upon receiving a normal select signal to switch from one clock to another the first clock continues as the output for a number of clock periods. The normal select signal is treated as a disconnect control signal only at the next positive edge of the first clock. The disconnect signal is delayed for a number of cycles and then applied to the control gate of the first clock only when a negative edge of the first clock is detected. Once the disconnect control signal has been issued and the first clock output is dead, the disconnect control signal starts the sequence for connecting the second clock to the output. The connect control signal is accepted at the next positive edge of the second clock, delaying the connect signal for a number of cycles and applying the connect signal to the control of the second clock only when a negative edge of the second clock is detected causing the second clock to disconnect from the output only at a negative edge.

Abstract: A system determines the root of a polynomial by employing a parallel structure that implements a Chien Search and minimizes the amount of storage required. The location of an error in a codeword can be derived from the root of an error locator polynomial. The performance of the Chien Search is enhanced by the parallel structure, and the location of the error can be easily determined using a simple calculation that preferably includes the cycle count, the parallelism, and the index of the multiplier/summer rank that indicates a root. Multiple ranks of multipliers receive data stored in a single array of data storage units. Multiplier values of each multiplier are based on the elements of a Galois Field. A method configures data storage units, multipliers, summers, and comparators, and performs a Chien Search. The location of an error in a codeword is determined using a simple calculation based on a determined root of an error locator polynomial.

Abstract: Apparatus, and an associated method, for performing error-correction operations to correct errors in a block of block-encoded data. Two ALUs are operable in parallel to perform finite-field mathematical operations and to calculate addresses used pursuant to the error-correction calculations. Instructions pursuant to which the ALUs are operable are stored in a memory device. The instructions are retrieved during operation of error-correcting calculations. The manner by which the error-correcting apparatus operates is alterable by appropriate alteration of the instructions stored at the memory device.

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first control signal and a second control signal in response to (i) a digital input signal and (ii) a clock signal. The second circuit may be configured to generate a third control signal by scrambling the first control signal. The third circuit may be configured to generate a pulse width modulated output signal in response to (i) the second control signal and (ii) the third control signal.

Abstract: Apparatus and an associated method calculates a CRC remainder for a block of data, such as a block of data retrieved from a CD-ROM device. CRC calculations are performed to provide assurances of data integrity subsequent to error corrections of the block of data. CRC remainders associated with N powers of two are stored in the look-up table. When calculating the CRC remainder, selected values stored in the look-up table are retrieved and combined to form the CRC remainder for the block of data.