Abstract: A transmitter/receiver module which includes circuitry for receiving serial digital data in diphase non-return-to-zero (NRZ) format and for demodulating said data into a separate synchronizing signal, data signal and clock signal and which further includes circuitry for transmitting the received and modulated signal or other modulated signals input directly to the module, such /transmitting circuitry including means for modulating the clock signal, data signal and synchronizing signal into the prescribed diphase NRZ format for output through a transformer coupled transmission line. The module further includes an oscillator for realigning the clock signal received with the serial digital data.

Abstract: A transmission line having a pair of wires enclosed in a shield is used to simultaneously transmit high frequency signals and low frequency power between distant locations. At the sending end of the line a high frequency source is connected between the first and second wires by circuitry which prevents the low frequency power from being coupled into the high frequency source. A low frequency power supply is connected between the shield and both of the wires by circuitry which prevents the high frequency signals from being coupled into the low frequency supply. At the receiving end of the transmission line circuitry is provided which separates the high frequency signals from the low frequency power.

Abstract: A clock phasing circuit for aligning data which is transmitted by a first clock, running at a particular frequency, with a second clock running at the same frequency as the first clock but in a different and undetermined phase relationship. The incoming data includes a synchronizing signal which initiates the operation of the clock phasing circuitry so that the data is alternately clocked into each of a pair of flip flops by successive pulses from the first clock. Each flip flop is individually connected to one of the inputs of one logic gate of a pair of gates which are alternately enabled by successive pulses from the second clock. The outputs from the two logic gates are combined by a further logic gate so that the data is reformed in alignment with the second clock.