Abstract: A memory circuit having a controllable output drive includes a storage circuit configured for at least temporarily storing a logical state of the memory circuit, and a drive control circuit coupled to the storage circuit. The drive control circuit is configurable for selectively controlling the output drive of the memory circuit.

Abstract: A test circuit for testing a first memory including a plurality of memory cells includes a first address decoder couplable to the first memory, the first address decoder configured for receiving a first input address and generating a first signal in response thereto for selectively accessing one or more of the memory cells in the first memory. The test circuit further includes a second memory including a plurality of memory cells and a second address decoder couplable to the second memory, the second address decoder configured for receiving a second input address and generating a second signal in response thereto for selectively accessing one or more of the memory cells in the second memory array.

Abstract: A test circuit for testing a first memory including a plurality of memory cells includes a first address decoder couplable to the first memory, the first address decoder configured for receiving a first input address and generating a first signal in response thereto for selectively accessing one or more of the memory cells in the first memory. The test circuit further includes a second memory including a plurality of memory cells and a second address decoder couplable to the second memory, the second address decoder configured for receiving a second input address and generating a second signal in response thereto for selectively accessing one or more of the memory cells in the second memory array.

Abstract: An asynchronous interface for coupling data between a terminal and a data module is provided. The asynchronous interface directly determines and matches to the rate of serial data being transmitted by the terminal and received by the data module with minimal involvement of a processor associated with the data module. The asynchronous interface determines the rate of the data being transmitted by configuring counting circuitry therein for measuring the period of the start bit in the first received character whenever the speed of data being transmitted by the terminal must be determined. The asynchronous interface then adjusts to the newly determined data rate and receives the remaining bits in the first character and subsequent characters at the new rate. The processor is involved only to request that the asynchronous interface determine the incoming data rate and match to it and, once the data rate has been determined and matched, to process the recovered characters and this new rate.