Patents by Inventor Mark Daniel Pogers

Mark Daniel Pogers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11972193
    Abstract: Disclosed herein are a method, a system, and a computer-readable storage-medium embodiments of automatic elastic CPU for a physical verification job. An embodiment includes generating multiple commands for a physical verification job of a design. The multiple commands are related by a dependency graph. The embodiment further includes allocating an initial amount of computing resources to execute the multiple commands, queuing a subset of the multiple commands for execution based on the dependency graph, adding an estimated amount of computing resources to the initial amount based on the number of the queued subset of commands and an estimated time to complete the queued subset of commands, and releasing a portion of the estimated amount of computing resources in response to the portion of the estimated amount of computing resources being idle for an amount of time greater than a target time.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: April 30, 2024
    Assignee: SYNOPSYS, INC.
    Inventors: Chris Allen Grossmann, Sumit Bhagwanani, Mark Daniel Pogers
  • Patent number: 11734489
    Abstract: A system, method, and computer readable medium with instructions for verifying an original layout are disclosed. The original layout includes cells arranged in a cell hierarchy, front-end-of-line (FEOL) layers, and back-end-of-line (BEOL) layers. In one embodiment, a reduced layout is generated by trimming out cells below a top tier of the cell hierarchy and filtering out the FEOL layers. A text-based short check is executed on the reduced layout. Next, an augmented reduced layout is generated. The augmented reduced layout includes pin information for cells in a second tier connected to the top tier. An interconnectivity check is then executed on the augmented reduced layout based on a schematic for the circuit. Afterwards, a result (e.g., location of short or connectivity mismatch) based on at least one of the text-based short check and the interconnectivity check is outputted. A conventional LVS check may then be executed.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: August 22, 2023
    Assignee: Synopsys, Inc.
    Inventors: Jinsik Yun, Mark Daniel Pogers, Jonathan Calvin White, Chiu-Yu Ku, Danny Chang, Lihhsing Ke
  • Publication number: 20210374322
    Abstract: A system, method, and computer readable medium with instructions for verifying an original layout are disclosed. The original layout includes cells arranged in a cell hierarchy, front-end-of-line (FEOL) layers, and back-end-of-line (BEOL) layers. In one embodiment, a reduced layout is generated by trimming out cells below a top tier of the cell hierarchy and filtering out the FEOL layers. A text-based short check is executed on the reduced layout. Next, an augmented reduced layout is generated. The augmented reduced layout includes pin information for cells in a second tier connected to the top tier. An interconnectivity check is then executed on the augmented reduced layout based on a schematic for the circuit. Afterwards, a result (e.g., location of short or connectivity mismatch) based on at least one of the text-based short check and the interconnectivity check is outputted. A conventional LVS check may then be executed.
    Type: Application
    Filed: June 2, 2021
    Publication date: December 2, 2021
    Inventors: Jinsik Yun, Mark Daniel Pogers, Jonathan Calvin White, Chiu-yu Ku, Danny Chang, Lihhsing Ke