Abstract: The exemplary embodiments are related to a device, a system, and a method for implementing a hardware mechanism that is configured to validate the performance of scheduling software utilized by a safety-critical system. The hardware device may receive an indication that a first frame of a frame schedule is in use. The hardware device may also monitor a time parameter corresponding to the first frame. The hardware device may also determine whether an indication that a second frame of the frame schedule is in use is received prior to the expiration of the time parameter. When the indication that the second frame of the frame scheduler is in use is not received prior to the expiration of time parameter, the hardware device may send a signal to an operating system of the safety-critical system indicating that an error in executing the frame scheduled has occurred.

Abstract: The exemplary embodiments are related to a device, a system, and a method for implementing a hardware mechanism that is configured to validate the performance of scheduling software utilized by a safety-critical system. The hardware device may receive an indication that a first frame of a frame schedule is in use. The hardware device may also monitor a time parameter corresponding to the first frame. The hardware device may also determine whether an indication that a second frame of the frame schedule is in use is received prior to the expiration of the time parameter. When the indication that the second frame of the frame scheduler is in use is not received prior to the expiration of time parameter, the hardware device may send a signal to an operating system of the safety-critical system indicating that an error in executing the frame scheduled has occurred.

Abstract: A computer readable storage medium storing a set of instructions executable by a processor. The set of instructions is operable to receive, from a first processor, a message to be sent to a second processor; store the message in a portion of a shared memory, the shared memory being shared by the first processor and the second processor; store, in an instruction list stored in a further portion of the shared memory, an instruction corresponding to the message; and prompt the second processor to read the message list.

Abstract: A device, system, and method processes a request for allocation of a resource of an electronic device utilizing a secure supervisor system call. The method includes receiving a call from a requesting application of the electronic device, the call indicating the request for allocation of the resource of the electronic device. The method includes determining whether the call is authorized to receive the resource of the electronic device. The determining includes determining whether the call includes a signature that is generated based upon a predetermined signature operation and determining whether the signature is valid based upon the predetermined signature operation when the call includes the signature. The method includes processing the request for the allocation of the resource when the call is determined to be authorized.

Abstract: A device, system, and method processes a request for allocation of a resource of an electronic device utilizing a secure supervisor system call. The method includes receiving a call from a requesting application of the electronic device, the call indicating the request for allocation of the resource of the electronic device. The method includes determining whether the call is authorized to receive the resource of the electronic device. The determining includes determining whether the call includes a signature that is generated based upon a predetermined signature operation and determining whether the signature is valid based upon the predetermined signature operation when the call includes the signature. The method includes processing the request for the allocation of the resource when the call is determined to be authorized.

Abstract: The exemplary embodiments described herein relate to systems and methods for improved process switching of a paravirtualized guest with a software-based memory management unit (“MMU”). One embodiment relates to a non-transitory computer readable storage medium including a set of instructions executable by a processor, the set of instructions, when executed, resulting in a performance of the following: create a plurality of new processes for each of a plurality of virtual environments, each of the virtual environments assigned one of a plurality of address space identifiers (“ASIDs”) stored in a cache memory, perform a process switch to one of the virtual environments thereby designating the one of the virtual environments as the active virtual environment, determine whether the active virtual environment has exhausted each of the ASIDs, and flush a cache memory when it is determined that the active virtual environment has exhausted each of the ASIDs.

Abstract: A computer readable storage medium storing a set of instructions executable by a processor. The set of instructions is operable to receive, from a first processor, a message to be sent to a second processor; store the message in a portion of a shared memory, the shared memory being shared by the first processor and the second processor; store, in an instruction list stored in a further portion of the shared memory, an instruction corresponding to the message; and prompt the second processor to read the message list.

Abstract: A scheduler of central processing unit (CPU) usage arranges tasks in a plurality of classes, associating a given task with a top level class and a sub-class. Weights may be associated with sub-classes and usage targets associated with top level classes. A target CPU usage may then be determined for the given task from a weight and a target CPU usage. Once an actual usage of the CPU by the given task is determined in a first predetermined evaluation interval, a penalty duration may be determined for the given task based on the actual usage and the target CPU usage. A penalty may then be applied to the given task for the penalty duration during a second predetermined evaluation interval.

Abstract: Described is a system which includes an error handler to generate an error record in response to a software error in an embedded device and a non-volatile memory including a persistent memory region configured to store an error log, the error log configured to receive the error record, wherein the error log remains intact in the non-volatile memory after a reboot of the embedded device.

Abstract: A scheduler of central processing unit (CPU) usage arranges tasks in a plurality of classes, associating a given task with a top level class and a sub-class. Weights may be associated with sub-classes and usage targets associated with top level classes. A target CPU usage may then be determined for the given task from a weight and a target CPU usage. Once an actual usage of the CPU by the given task is determined in a first predetermined evaluation interval, a penalty duration may be determined for the given task based on the actual usage and the target CPU usage. A penalty may then be applied to the given task for the penalty duration during a second predetermined evaluation interval.