Abstract: An example of an apparatus to transport utility-scale lithium-ion batteries in a racked and operational state. The apparatus includes a base and an isolation platform. In addition, the apparatus includes an isolator mounted on the base to support the isolation platform. The isolator is to dampen forces exerted on the isolation platform from the base. Furthermore, the apparatus includes a rack mounted onto the isolation platform. The rack is to secure a plurality of lithium-ion batteries to store energy at a utility-scale to be provided to a power distribution network. The plurality of lithium-ion batteries is racked in an operational state during transportation.

Abstract: A method, an apparatus, and a computer program are provided to account for data stored in Dynamic Random Access Memory (DRAM) write buffers. There is difficulty in tracking the data stored in DRAM write buffers. To alleviate the difficulty, a cache line list is employed. The cache line list is maintained in a memory controller, which is updated with data movement. This list allows for ease of maintenance of data without loss of consistency.

Abstract: A mechanism is provided to reuse functional data buffers. With Extreme Data Rate (XDR™) Dynamic Random Access Memory (DRAM), test patterns are employed to dynamically calibrate data with the clock. To perform this task, data buffers are employed to store data and commands for the calibration patterns. However, there are different procedures and requirements for transmission and reception calibrations. Hence, to reduce the amount of hardware needed to perform transmission and reception calibrations, the data buffers employ additional front end circuitry to reuse the buffers for both tasks.

Abstract: In an aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) generating a first command and associated address of a first type that does not indicate a rank of memory targeted by the first command; (2) determining whether the memory includes a plurality of ranks; (3) if the memory includes a plurality of ranks, employing the processor to update the address associated with the first command to indicate a memory rank targeted by the first command; (4) if the memory does not include a plurality of ranks, employing the processor to update the address associated with the first command to indicate the memory does not include a plurality of ranks; and (5) converting the first command and associated updated address to a second command and associated address that are employed to access the memory. Numerous other aspects are provided.

Abstract: The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access.

Abstract: Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.

Abstract: A method and apparatus are provided for scaling an input bandwidth for bandwidth allocation technology. An original bandwidth count value of an input flow is received. A bandwidth scaler constant is provided and used for scaling the received original bandwidth count value to provide a scaled bandwidth value between zero and one. The scaled bandwidth value is stored and used for calculating a transmit probability for the input flow.

Abstract: A method and apparatus are provided for implementing bus interface calibration to improve bus interface initialization time in a system. Bus interface calibration is performed and average calibration values are saved. At bus interface initialization time, checking for saved calibration values is performed. The saved calibration values are used and tested. When the saved calibration values pass the test, then the saved calibration values are used for system operation without performing any training steps.

Abstract: A mechanism provided for controlling a transmission enable (TX_ENA) signal. The mechanism generates a queue of bits to track a sequence of commands and provides the transmit enable signal if the queue is empty. If an entry at a top of the queue indicates a write command, the mechanism provides the transmit enable signal for a predetermined number of cycles before the transmit enable signal is needed and until write data associated with the entry is transmitted, whereupon the entry is removed from the queue. If the entry at the top of the queue does not indicate a write command, the mechanism discontinues the transmit enable signal and removing the entry from the queue.

Abstract: A memory system employs calibrations to ensure the precise transmission of data. During calibrations, memory refreshes can occur; however, these refreshes can interfere with calibration streams. Therefore, to alleviate collisions and interferences, refreshes are deferred to periods where no calibrations are taking place. The number of deferred refreshes is also tracked such that the overall loss of refreshes is prevented.

Abstract: A structure of sequencers, a method, and a computer program are provided for performing initial and periodic calibrations in an XDR™ memory system. A memory controller that performs these calibrations is divided into identical, independent halves, with each half containing a Current/Impedance Calibration (i/z Cal) sequencer and six Bank sequencers. The i/z Cal sequencer contains three pathways that perform the XIO current and termination calibrations, and the XDR™ DRAM current and termination impedance calibrations. Each Bank sequencer contains normal read and write operation pathways that are reused to accomplish receive setup, receive hold, transmit setup, transmit hold, XIO receive, and XIO transmit timing calibrations. Initial and periodic calibrations are necessary to ensure the precise transfer of data between the XIOs and the XDR™ DRAMs.

Abstract: Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.

Abstract: A memory controller design tool retrieves parameter ranges supported by a memory controller, and identifies troublesome parameter value combinations. The memory controller design tool suggests to 1) add logic to the memory controller to resolve the conflict, 2) incorporate a constraint that reduces/eliminates command collisions, data conflicts, and/or the need to check particular timing parameters, or 3) a combination of both. The memory controller design tool may work in conjunction with a memory controller designer to define and use the constraints.

Abstract: Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.

Abstract: The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access.

Abstract: The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access.

Abstract: In a first aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) providing a processor adapted to issue a command complying with a first protocol; (2) providing a memory coupled to the processor and accessible by a command complying with a second protocol; (3) employing a plurality of scrub commands complying with the second protocol to check respective portions of the memory for errors, wherein each scrub command complying with the second protocol is a converted version of a scrub command complying with the first protocol issued by the processor and the respective portions are non-sequential; and (4) refreshing bits stored in the entire memory within a predetermined time period. Numerous other aspects are provided.

Abstract: In an aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) generating a first command and associated address of a first type that does not indicate a rank of memory targeted by the first command; (2) determining whether the memory includes a plurality of ranks; (3) if the memory includes a plurality of ranks, employing the processor to update the address associated with the first command to indicate a memory rank targeted by the first command; (4) if the memory does not include a plurality of ranks, employing the processor to update the address associated with the first command to indicate the memory does not include a plurality of ranks; and (5) converting the first command and associated updated address to a second command and associated address that are employed to access the memory. Numerous other aspects are provided.

Abstract: In a first aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) providing a computer system including (a) a memory; (b) a processor adapted to issue a functional command to the memory; (c) a translation chip; (d) a first link adapted to couple the processor to the translation chip; and (e) a second link adapted to couple the translation chip to the memory; (2) calibrating the first link using the translation chip; and (3) while calibrating the first link, calibrating the second link using the translation chip. Numerous other aspects are provided.

Abstract: In a first aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) providing a computer system including (a) a first memory; (b) a processor adapted to issue a functional command to the first memory; (c) a translation chip; (d) a cache memory coupled to the translation chip; (e) a first link adapted to couple the processor to the translation chip; and (f) a second link adapted to couple the translation chip to the first memory; and (2) calibrating the first link to transmit data between the processor and cache memory. Numerous other aspects are provided.