Abstract: For simulation of a multiprocessor system having a multi-level cache hierarchy, possible and legal cache coherency state combinations are classified based on the state of one level one cache, and subclassified within the major classes to define unique combinations, a number significantly less than the number of all possible combinations. For data words in the test case, a cache coherency state combination is randomly selected from a combination table listing all subclasses. Stale data generated by inverting all or part of the original data from the test case may be preloaded with the coherency states as necessary. Existing coherency is maintained when test case data is preloaded to a cache location already preloaded to avoid previously loaded stale data from becoming valid with the new coherency state. Coherency state combinations which are preloaded are tracked to help ensure that all subclasses an are preloaded and tested during simulation prior to tapeout.