Patents by Inventor Mark David Jaffe
Mark David Jaffe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180204926Abstract: Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator on the substrate, and a gate conductor on the gate insulator. First and second sections of the gate conductor are within the active region of the substrate, while a third section is in the isolation region of the substrate. The second section of the gate conductor tapers from the width of the first section to the width of the wider third section. The first section and the second section of the gate conductor have undercut regions where the corner of the gate conductor contacts the substrate. The third section of the gate conductor lacks the undercut regions. The gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the gate conductor lacks the undercut regions in the isolation region.Type: ApplicationFiled: March 15, 2018Publication date: July 19, 2018Applicant: GLOBALFOUNDRIES INC.Inventors: Michel J. Abou-Khalil, Alan Bernard Botula, Blaine Jeffrey Gross, Mark David Jaffe, Alvin Joseph, Richard A. Phelps, Steven M. Shank, James Albert Slinkman
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Patent number: 9978849Abstract: Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator on the substrate, and a gate conductor on the gate insulator. First and second sections of the gate conductor are within the active region of the substrate, while a third section is in the isolation region of the substrate. The second section of the gate conductor tapers from the width of the first section to the width of the wider third section. The first section and the second section of the gate conductor have undercut regions where the corner of the gate conductor contacts the substrate. The third section of the gate conductor lacks the undercut regions. The gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the gate conductor lacks the undercut regions in the isolation region.Type: GrantFiled: December 29, 2015Date of Patent: May 22, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Michel J. Abou-Khalil, Alan Bernard Botula, Blaine Jeffrey Gross, Mark David Jaffe, Alvin Joseph, Richard A. Phelps, Steven M. Shank, James Albert Slinkman
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Publication number: 20170186845Abstract: Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator on the substrate, and a gate conductor on the gate insulator. First and second sections of the gate conductor are within the active region of the substrate, while a third section is in the isolation region of the substrate. The second section of the gate conductor tapers from the width of the first section to the width of the wider third section. The first section and the second section of the gate conductor have undercut regions where the corner of the gate conductor contacts the substrate. The third section of the gate conductor lacks the undercut regions. The gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the gate conductor lacks the undercut regions in the isolation region.Type: ApplicationFiled: December 29, 2015Publication date: June 29, 2017Applicant: GLOBALFOUNDRIES INC.Inventors: Michel J. Abou-Khalil, Alan Bernard Botula, Blaine Jeffrey Gross, Mark David Jaffe, Alvin Joseph, Richard A. Phelps, Steven M. Shank, James Albert Slinkman
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Patent number: 8471306Abstract: A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.Type: GrantFiled: July 28, 2011Date of Patent: June 25, 2013Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Timothy Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Stephen Ellinwood Luce, Anthony Kendall Stamper
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Patent number: 8421126Abstract: Semiconductor structures. The semiconductor structures include two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers or bonding them back to back utilizing an inter-substrate dielectric layer and a bonding layer between the buried oxide layers. The structures include contacts formed in the upper wafer to devices in the lower wafer and wiring levels formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.Type: GrantFiled: June 20, 2011Date of Patent: April 16, 2013Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Timothy Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Stephen Ellinwood Luce, Anthony Kendall Stamper
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Patent number: 8138531Abstract: Pixel sensor cells, method of fabricating pixel sensor cells and design structure for pixel sensor cells. The pixel sensor cells including: a photodiode body in a first region of a semiconductor layer; a floating diffusion node in a second region of the semiconductor layer, a third region of the semiconductor layer between and abutting the first and second regions; and dielectric isolation in the semiconductor layer, the dielectric isolation surrounding the first, second and third regions, the dielectric isolation abutting the first, second and third regions and the photodiode body, the dielectric isolation not abutting the floating diffusion node, portions of the second region intervening between the dielectric isolation and the floating diffusion node.Type: GrantFiled: September 17, 2009Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: James William Adkisson, John Joseph Ellis-Monaghan, Mark David Jaffe, Richard John Rassel
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Publication number: 20110302542Abstract: A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.Type: ApplicationFiled: July 28, 2011Publication date: December 8, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kerry Bernstein, Timothy Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Stephen Ellinwood Luce, Anthony Kendall Stamper
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Publication number: 20110241082Abstract: A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.Type: ApplicationFiled: June 20, 2011Publication date: October 6, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kerry Bernstein, Timothy Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Stephen Ellinwood Luce, Anthony Kendall Stamper
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Patent number: 8013342Abstract: A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.Type: GrantFiled: November 14, 2007Date of Patent: September 6, 2011Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Timothy Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Stephen Ellinwood Luce, Anthony Kendall Stamper
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Patent number: 8004289Abstract: Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10?18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.Type: GrantFiled: August 26, 2008Date of Patent: August 23, 2011Assignee: International Business Machines CorporationInventors: Thomas Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Stephen Ellinwood Luce, Edmund Juris Sprogis
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Patent number: 7989312Abstract: A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.Type: GrantFiled: November 5, 2009Date of Patent: August 2, 2011Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Timothy Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Stephen Ellinwood Luce, Anthony Kendall Stamper
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Patent number: 7960245Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.Type: GrantFiled: February 12, 2008Date of Patent: June 14, 2011Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Timothy Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Anthony Kendall Stamper
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Patent number: 7939914Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.Type: GrantFiled: February 12, 2008Date of Patent: May 10, 2011Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Timothy Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Anthony Kendall Stamper
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Publication number: 20110062542Abstract: Pixel sensor cells, method of fabricating pixel sensor cells and design structure for pixel sensor cells. The pixel sensor cells including: a photodiode body in a first region of a semiconductor layer; a floating diffusion node in a second region of the semiconductor layer, a third region of the semiconductor layer between and abutting the first and second regions; and dielectric isolation in the semiconductor layer, the dielectric isolation surrounding the first, second and third regions, the dielectric isolation abutting the first, second and third regions and the photodiode body, the dielectric isolation not abutting the floating diffusion node, portions of the second region intervening between the dielectric isolation and the floating diffusion node.Type: ApplicationFiled: September 17, 2009Publication date: March 17, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James William Adkisson, John Joseph Ellis-Monaghan, Mark David Jaffe, Richard John Rassel
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Patent number: 7863734Abstract: An electronic device and method of packaging an electronic device. The device including: a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads on the second side of the integrated circuit chip, chip pads of the first set of chip pads physically and electrically connected to corresponding substrate pads on the first substrate and chip pads of the second set of chip pads physically and electrically connected to substrate pads of the substrate.Type: GrantFiled: August 6, 2008Date of Patent: January 4, 2011Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Timothy Dalton, Timothy Harrison Daubenspeck, Jeffrey Peter Gambino, Mark David Jaffe, Christopher David Muzzy, Wolfgang Sauter, Edmund Sprogis, Anthony Kendall Stamper
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Patent number: 7670927Abstract: A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.Type: GrantFiled: May 16, 2006Date of Patent: March 2, 2010Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Timothy Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Stephen Ellinwood Luce, Anthony Kendall Stamper
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Publication number: 20100044759Abstract: A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.Type: ApplicationFiled: November 5, 2009Publication date: February 25, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kerry Bernstein, Timothy Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Stephen Ellinwood Luce, Anthony Kendall Stamper
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Publication number: 20090121287Abstract: A semiconductor device having wiring levels on opposite sides, a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides, and a design structure of a semiconductor device having wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.Type: ApplicationFiled: November 14, 2007Publication date: May 14, 2009Inventors: Kerry Bernstein, Timothy Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Anthony Kendall Stamper
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Publication number: 20090121260Abstract: A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.Type: ApplicationFiled: November 14, 2007Publication date: May 14, 2009Inventors: Kerry Bernstein, Timothy Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Stephen Ellinwood Luce, Anthony Kendall Stamper
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Publication number: 20090065925Abstract: An electronic device and method of packaging an electronic device. The device including: a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads on the second side of the integrated circuit chip, chip pads of the first set of chip pads physically and electrically connected to corresponding substrate pads on the first substrate and chip pads of the second set of chip pads physically and electrically connected to substrate pads of the substrate.Type: ApplicationFiled: August 6, 2008Publication date: March 12, 2009Inventors: Kerry Bernstein, Timothy Dalton, Timothy Harrison Daubenspeck, Jeffrey Peter Gambino, Mark David Jaffe, Christopher David Muzzy, Wolfgang Sauter, Edmund Sprogis, Anthony Kendall Stamper