Patents by Inventor Mark David Lippett
Mark David Lippett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220137962Abstract: A processor comprising a register file comprising a bias register for holding a bias and a plurality of operand registers each for holding a respective number which together with the bias represents a respective value in a logarithmic number system; and an execution unit configured to, in response to receiving a logarithmic addition opcode: retrieve first and second numbers from first and second sources respectively; subtract the first number from the second number to determine a difference; and if the determined difference is less than or equal to a predetermined number, retrieve, from a look-up table, a third number mapped to the determined difference, and add the third number to the first number to determine a result; if the determined difference is greater than the predetermined number, determine the result to be the greatest of the first and second numbers; and store the result.Type: ApplicationFiled: February 14, 2020Publication date: May 5, 2022Applicant: XMOS LTDInventors: Hendkik Lambertus MULLER, Mark David LIPPETT
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Patent number: 10268609Abstract: A resource management and task allocation controller for installation in a multicore processor having a plurality of interconnected processor elements providing resources for processing executable transactions, at least one of said elements being a master processing unit, the controller being adapted to communicate, when installed, with each of the processor elements including the master processing unit, and comprising control logic for allocating executable transactions within the multicore processor to particular processor elements in accordance with pre-defined allocation parameters.Type: GrantFiled: August 12, 2013Date of Patent: April 23, 2019Assignees: Synopsys, Inc., Fujitsu Semiconductor LimitedInventor: Mark David Lippett
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Patent number: 9830241Abstract: A method of monitoring thread execution within a multicore processor architecture which comprises a plurality of interconnected processor elements for processing the threads, the method comprising receiving a plurality of thread parameter indicators of one or more parameters relating to the function and/or identity and/or execution location of a thread or threads, comparing at least one of the thread parameter indicators with a first plurality of predefined criteria each representative of an indicator of interest, and generating an output consequential upon thread parameter indicators which have been identified to be of interest as a result of the said comparison.Type: GrantFiled: August 10, 2015Date of Patent: November 28, 2017Assignees: Synopsys, Inc., Fujitsu Semiconductor LimitedInventors: Mark David Lippett, Ayewin Oung
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Patent number: 9779042Abstract: A resource management and task allocation controller for installation in a multicore processor having a plurality of interconnected processor elements providing resources for processing executable transactions, at least one of said elements being a master processing unit, the controller being adapted to communicate, when installed, with each of the processor elements including the master processing unit, and comprising control logic for allocating executable transactions within the multicore processor to particular processor elements in accordance with pre-defined allocation parameters.Type: GrantFiled: August 12, 2013Date of Patent: October 3, 2017Assignees: Synopsys, Inc., Fujitsu Semiconductor LimitedInventor: Mark David Lippett
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Patent number: 9442886Abstract: This invention relates to scheduling threads in a multicore processor. Executable transactions may be scheduled using at least one distribution queue, which lists executable transactions in order of eligibility for execution, and multilevel scheduler which comprises a plurality of linked individual executable transaction schedulers. Each of these includes a scheduling algorithm for determining the most eligible executable transaction for execution. The most eligible executable transaction is outputted from the multilevel scheduler to the at least one distribution queue.Type: GrantFiled: September 9, 2015Date of Patent: September 13, 2016Assignees: Synopsys, Inc., Fujitsu Semiconductor LimitedInventor: Mark David Lippett
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Patent number: 9286262Abstract: The disclosure relates to scheduling threads in a multicore processor. Executable transactions may be scheduled using at least one distribution queue, which lists executable transactions in order of eligibility for execution, and multilevel scheduler which comprises a plurality of linked individual executable transaction schedulers. Each of these includes a scheduling algorithm for determining the most eligible executable transaction for execution. The most eligible executable transaction is outputted from the multilevel scheduler to the at least one distribution queue.Type: GrantFiled: April 4, 2014Date of Patent: March 15, 2016Assignees: Synopsys, Inc., Fujitsu Semiconductor LimitedInventor: Mark David Lippett
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Publication number: 20150378776Abstract: This invention relates to scheduling threads in a multicore processor. Executable transactions may be scheduled using at least one distribution queue, which lists executable transactions in order of eligibility for execution, and multilevel scheduler which comprises a plurality of linked individual executable transaction schedulers. Each of these includes a scheduling algorithm for determining the most eligible executable transaction for execution. The most eligible executable transaction is outputted from the multilevel scheduler to the at least one distribution queue.Type: ApplicationFiled: September 9, 2015Publication date: December 31, 2015Inventor: Mark David Lippett
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Publication number: 20150347255Abstract: A method of monitoring thread execution within a multicore processor architecture which comprises a plurality of interconnected processor elements for processing the threads, the method comprising receiving a plurality of thread parameter indicators of one or more parameters relating to the function and/or identity and/or execution location of a thread or threads, comparing at least one of the thread parameter indicators with a first plurality of predefined criteria each representative of an indicator of interest, and generating an output consequential upon thread parameter indicators which have been identified to be of interest as a result of the said comparison.Type: ApplicationFiled: August 10, 2015Publication date: December 3, 2015Inventors: Mark David Lippett, Ayewin Oung
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Patent number: 9164953Abstract: This invention relates to scheduling threads in a multicore processor. Executable transactions may be scheduled using at least one distribution queue, which lists executable transactions in order of eligibility for execution, and multilevel scheduler which comprises a plurality of linked individual executable transaction schedulers. Each of these includes a scheduling algorithm for determining the most eligible executable transaction for execution. The most eligible executable transaction is outputted from the multilevel scheduler to the at least one distribution queue.Type: GrantFiled: May 1, 2014Date of Patent: October 20, 2015Assignees: Synopsys, Inc., Fujitsu Semiconductor LimitedInventor: Mark David Lippett
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Patent number: 9129050Abstract: A method of monitoring thread execution within a multicore processor architecture which comprises a plurality of interconnected processor elements for processing the threads, the method comprising receiving a plurality of thread parameter indicators of one or more parameters relating to the function and/or identity and/or execution location of a thread or threads, comparing at least one of the thread parameter indicators with a first plurality of predefined criteria each representative of an indicator of interest, and generating an output consequential upon thread parameter indicators which have been identified to be of interest as a result of the said comparison.Type: GrantFiled: August 12, 2013Date of Patent: September 8, 2015Assignees: Synopys, Inc., Fujitsu Semiconductor LimitedInventors: Mark David Lippett, Ayewin Oung
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Patent number: 9038070Abstract: According to a first aspect of the present invention, there is provided a method of monitoring thread execution within a multicore processor architecture which comprises a plurality of interconnected processor elements for processing the threads, the method comprising receiving a plurality of thread parameter indicators indicative of one or more parameters relating to the function and/or identity of a thread or threads comparing at least some of the thread parameter indicators with a first plurality of predefined criteria each representative of an indicator of interest and generating an output consequential upon thread parameter indicators which have been identified to be of interest as a result of the said comparison.Type: GrantFiled: September 14, 2004Date of Patent: May 19, 2015Assignees: Synopsys, Inc., Fujitsu Semiconductor LimitedInventors: Mark David Lippett, Ayewin Oung
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Patent number: 9038076Abstract: A method of monitoring thread execution within a multicore processor architecture which comprises a plurality of interconnected processor elements for processing the threads, the method comprising receiving a plurality of thread parameter indicators of one or more parameters relating to the function and/or identity and/or execution location of a thread or threads, comparing at least one of the thread parameter indicators with a first plurality of predefined criteria each representative of an indicator of interest, and generating an output consequential upon thread parameter indicators which have been identified to be of interest as a result of the said comparison.Type: GrantFiled: August 12, 2013Date of Patent: May 19, 2015Assignees: Synopsys, Inc., Fujitsu Semiconductor LimitedInventors: Mark David Lippett, Ayewin Oung
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Publication number: 20140317378Abstract: This invention relates to scheduling threads in a multicore processor. Executable transactions may be scheduled using at least one distribution queue, which lists executable transactions in order of eligibility for execution, and multilevel scheduler which comprises a plurality of linked individual executable transaction schedulers. Each of these includes a scheduling algorithm for determining the most eligible executable transaction for execution. The most eligible executable transaction is outputted from the multilevel scheduler to the at least one distribution queue.Type: ApplicationFiled: May 1, 2014Publication date: October 23, 2014Applicants: Synopsys, Inc., Fujitsu Semiconductor LimitedInventor: Mark David Lippett
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Publication number: 20140282593Abstract: The disclosure relates to scheduling threads in a multicore processor. Executable transactions may be scheduled using at least one distribution queue, which lists executable transactions in order of eligibility for execution, and multilevel scheduler which comprises a plurality of linked individual executable transaction schedulers. Each of these includes a scheduling algorithm for determining the most eligible executable transaction for execution. The most eligible executable transaction is outputted from the multilevel scheduler to the at least one distribution queue.Type: ApplicationFiled: April 4, 2014Publication date: September 18, 2014Applicant: Synopsys, Inc.Inventor: Mark David Lippett
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Patent number: 8751773Abstract: This invention relates to scheduling threads in a multicore processor. Executable transactions may be scheduled using at least one distribution queue, which lists executable transactions in order of eligibility for execution, and multilevel scheduler which comprises a plurality of linked individual executable transaction schedulers. Each of these includes a scheduling algorithm for determining the most eligible executable transaction for execution. The most eligible executable transaction is outputted from the multilevel scheduler to the at least one distribution queue.Type: GrantFiled: August 12, 2013Date of Patent: June 10, 2014Assignees: Synopsys, Inc., Fujitsu Semiconductor LimitedInventor: Mark David Lippett
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Publication number: 20140068619Abstract: This invention relates to scheduling threads in a multicore processor. Executable transactions may be scheduled using at least one distribution queue, which lists executable transactions in order of eligibility for execution, and multilevel scheduler which comprises a plurality of linked individual executable transaction schedulers. Each of these includes a scheduling algorithm for determining the most eligible executable transaction for execution. The most eligible executable transaction is outputted from the multilevel scheduler to the at least one distribution queue.Type: ApplicationFiled: August 12, 2013Publication date: March 6, 2014Applicant: Synopsys, Inc.Inventor: Mark David Lippett
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Publication number: 20140026141Abstract: A resource management and task allocation controller for installation in a multicore processor having a plurality of interconnected processor elements providing resources for processing executable transactions, at least one of said elements being a master processing unit, the controller being adapted to communicate, when installed, with each of the processor elements including the master processing unit, and comprising control logic for allocating executable transactions within the multicore processor to particular processor elements in accordance with pre-defined allocation parameters.Type: ApplicationFiled: August 12, 2013Publication date: January 23, 2014Applicant: Synopsys, Inc.Inventor: Mark David Lippett
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Publication number: 20140025857Abstract: A resource management and task allocation controller for installation in a multicore processor having a plurality of interconnected processor elements providing resources for processing executable transactions, at least one of said elements being a master processing unit, the controller being adapted to communicate, when installed, with each of the processor elements including the master processing unit, and comprising control logic for allocating executable transactions within the multicore processor to particular processor elements in accordance with pre-defined allocation parameters.Type: ApplicationFiled: August 12, 2013Publication date: January 23, 2014Applicant: Synopsys, Inc.Inventor: Mark David Lippett
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Publication number: 20130326282Abstract: A method of monitoring thread execution within a multicore processor architecture which comprises a plurality of interconnected processor elements for processing the threads, the method comprising receiving a plurality of thread parameter indicators of one or more parameters relating to the function and/or identity and/or execution location of a thread or threads, comparing at least one of the thread parameter indicators with a first plurality of predefined criteria each representative of an indicator of interest, and generating an output consequential upon thread parameter indicators which have been identified to be of interest as a result of the said comparison.Type: ApplicationFiled: August 12, 2013Publication date: December 5, 2013Applicant: Synopsys, Inc.Inventors: Mark David Lippett, Ayewin Oung
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Publication number: 20130326283Abstract: A method of monitoring thread execution within a multicore processor architecture which comprises a plurality of interconnected processor elements for processing the threads, the method comprising receiving a plurality of thread parameter indicators of one or more parameters relating to the function and/or identity and/or execution location of a thread or threads, comparing at least one of the thread parameter indicators with a first plurality of predefined criteria each representative of an indicator of interest, and generating an output consequential upon thread parameter indicators which have been identified to be of interest as a result of the said comparison.Type: ApplicationFiled: August 12, 2013Publication date: December 5, 2013Applicant: Synopsys, Inc.Inventors: Mark David Lippett, Ayewin Oung