Abstract: Creating security enclaves includes determining one or more parameters of one or more applications and one or more services operating in the network. An optimal number of clusters for grouping the one or more applications and the one or more services is determined based on the one or more parameters. Then, the one or more applications and the one or more services are grouped into the clusters and one or more security enclaves are applied to each of the clusters so as to maximize operational security of the network.

Abstract: Creating security enclaves includes determining one or more parameters of one or more applications and one or more services operating in the network. An optimal number of clusters for grouping the one or more applications and the one or more services is determined based on the one or more parameters. Then, the one or more applications and the one or more services are grouped into the clusters and one or more security enclaves are applied to each of the clusters so as to maximize operational security of the network.

Abstract: A method, system, and computer program product for improving system performance using cooling configuration information are provided in the illustrative embodiments. A set of components in a data processing system is indexed according to corresponding amounts of cooling available to the components in the set. Priorities are assigned to component users in a set of component users. Using a processor and a memory, a component whose index value represents a higher than threshold amount of cooling availability to the component is allocated to a component user whose priority is higher than a threshold priority.

Abstract: A method, system, and computer program product for improving system performance using cooling configuration information are provided in the illustrative embodiments. A set of components in a data processing system is indexed according to corresponding amounts of cooling available to the components in the set. Priorities are assigned to component users in a set of component users. Using a processor and a memory, a component whose index value represents a higher than threshold amount of cooling availability to the component is allocated to a component user whose priority is higher than a threshold priority.

Abstract: A method, system, and computer usable program product for a self-tuning I/O device are provided in the illustrative embodiments. A change is detected in an adapter communicating with the I/O device, the I/O device being a consolidator configured to communicate with the adapter in a data network. A type of the adapter is determined. Values for each parameter in a set of parameters corresponding to the type of the adapter are determined. The values of a first subset of the parameters are applied to the consolidator, applying the values of the first subset causing the consolidator to be configured to operate in a preferred configuration with the adapter.

Abstract: A method, system, and computer usable program product for a self-tuning I/O device are provided in the illustrative embodiments. A change is detected in an adapter communicating with the I/O device, the I/O device being a consolidator configured to communicate with the adapter in a data network. A type of the adapter is determined. Values for each parameter in a set of parameters corresponding to the type of the adapter are determined. The values of a first subset of the parameters are applied to the consolidator, applying the values of the first subset causing the consolidator to be configured to operate in a preferred configuration with the adapter.

Abstract: A computer implemented method, apparatus, and computer program product for managing symmetric multiprocessor interconnects. The process identifies functional communication connections between each processor in a plurality of processors on a multiprocessor to form identified functional communication connections. The process maps every functional communication connection between any two processors in the plurality of processors, based on the identified functional communication connections, to form an interconnect matrix. The process creates a path map using the interconnect matrix. The path map comprises a sequence of communication connections between the plurality of processors. The process initializes the plurality of processors using the path map.

Abstract: A computer implemented method and system for enhancing boot time of a computer system. Initial program load firmware is initialized on a plurality of service processors. The plurality of service processors performs independent non-redundant initialization tasks concurrently as other independent non-redundant initialization tasks are performed by another service processor. Once the initialization tasks are completed, control is switched to a primary service processor within the plurality of service processors and runtime firmware is loaded by the primary service processor.

Abstract: A method, apparatus, and computer instructions for self-diagnosing remote I/O enclosures with enhanced FRU callouts. when a failure is detected on a RIO drawer, a data processing system uses the bulk power controller to provide an alternate path, rather than using the existing RIO links, to access registers on the I/O drawers. The system logs onto the bulk power controller, which provides a communications path between the data processing system and the RIO drawer. The communications path allows the data processing system to read all of the registers on the I/O drawer. The register information in the I/O drawer is then analyzed to diagnose the I/O failure. Based on the register information, the data processing system identifies a field replacement unit to repair the I/O failure.

Abstract: A method, apparatus, and computer instructions for self-diagnosing remote I/O enclosures with enhanced FRU callouts. When a failure is detected on a RIO drawer, a data processing system uses the bulk power controller to provide an alternate path, rather than using the existing RIO links, to access registers on the I/O drawers. The system logs onto the bulk power controller, which provides a communications path between the data processing system and the RIO drawer. The communications path allows the data processing system to read all of the registers on the I/O drawer. The register information in the I/O drawer is then analyzed to diagnose the I/O failure. Based on the register information, the data processing system identifies a field replacement unit to repair the I/O failure.

Abstract: A method for self-diagnosing remote I/O enclosures with enhanced FRU callouts. When a failure is detected on a RIO drawer, a data processing system uses the bulk power controller to provide an alternate path, rather than using the existing RIO links, to access registers on the I/O drawers. The system logs onto the bulk power controller, which provides a communications path between the data processing system and the RIO drawer. The communications path allows the data processing system to read all of the registers on the I/O drawer. The register information in the I/O drawer is then analyzed to diagnose the I/O failure. Based on the register information, the data processing system identifies a field replacement unit to repair the I/O failure.

Abstract: A data processing system includes multiple processors each having multiple processor cores. A core checkstop from a particular processor core indicates that a memory array associated with the particular core exhibits an error. In response to the core checkstop, the system migrates the workload of the particular processor core to another processor core. The system also removes the particular processor core from the current configuration of the system. In response to the core checkstop and error, the system initializes the particular processor core if the error is in a processor memory array associated with the particular core. The system then attempts correction of the error with array built-in self test (ABIST) circuitry. If the ABIST succeeds in correcting the error, the initialization of the particular processor core completes and the system returns the particular processor core to the current processor configuration.

Abstract: A computer implemented method, apparatus, and computer program product for managing symmetric multiprocessor interconnects. The process identifies functional communication connections between each processor in a plurality of processors on a multiprocessor to form identified functional communication connections. The process maps every functional communication connection between any two processors in the plurality of processors, based on the identified functional communication connections, to form an interconnect matrix. The process creates a path map using the interconnect matrix. The path map comprises a sequence of communication connections between the plurality of processors. The process initializes the plurality of processors using the path map.

Abstract: A method, system, and computer product for aiding in the debugging of an I/O failure. When an I/O failure is detected on a RIO drawer, a data processing system uses the bulk power controller to provide an alternate path, rather than using the existing RIO links, to access registers on the I/O drawers. The system logs onto the bulk power controller, which provides a communications path between the data processing system and the RIO drawer. The communications path allows the data processing system to read the chip registers on the I/O drawer. The data processing system captures I/O failure information in the I/O drawer using the communications path, wherein the I/O failure information is used to debug the I/O failure.

Abstract: A non-invasive method, system, and computer product for monitoring I/O performance without using the RIO bus. When executing a performance benchmark run in a remote I/O drawer, the system logs into a bulk power controller, wherein the bulk power controller provides a communications path between the data processing system and the I/O drawer, and wherein the communications path allows the data processing system to access chip register information on the I/O drawer without using a RIO link. Using the communications path, the system may monitor I/O performance and obtain chip register information. The system may further increase performance by using software to detect a load imbalance. Through the communications path, the software is able to dynamically balance the load by changing the chip register settings to allow the initialization registers to handle the load more efficiently.

Abstract: A modified system causes the REQ64# signal to be asserted when the adapter is in reset on a 64-bit slot. This allows the adapter to see that it is in a 64-bit slot at the beginning of reset, preventing the adapter from driving the 64-bit extension pins. The above-described modification must be made to all the 64-bit slots on a system. When the reset signal is active, it will cause the buffer to drive the REQ64# signal low. This will synchronize reset and REQ64#, eliminating the possibility for bus contention. No modification is necessary for 32-bit slots. This modification will not affect the normal operation of the bus, since it is only used during reset.