Abstract: The invention provides an architecture and method for implementing a programmable I/O interface. The primary function provides a generic reconfigurable interface for serial communications between a laser printer controller and the print mechanism. The design also supports vertical page synchronization (top of page detection).

Abstract: The invention provides an architecture and method for implementing a programmable I/O interface. The primary function provides a generic reconfigurable interface for serial communications between a laser printer controller and the print mechanism. The design also supports vertical page synchronization (top of page detection).

Abstract: In accordance with the invention, it has been determined that the bandwidth, guaranteed periodic delivery and error correction characteristics of a USB High-Speed Interrupt OUT pipe of the USB 2.0 standard enable the Interrupt OUT pipe to be used to transfer print data from the host computer to the printer. By using the Interrupt OUT pipe for this purpose, it is no longer necessary to store an entire rasterized page in the formatter memory of the printer before commencing printing of the page. Consequently, the size of the formatter memory device can be relatively small compared to the size of the formatter memory device that is currently used to store an entire rasterized page. Alternatively, the same size memory device as that currently used to store an entire rasterized page may be used to enable higher resolution pages to be printed.

Abstract: The invention provides an architecture and method for implementing a programmable I/O interface. The primary function provides a generic reconfigurable interface for serial communications between a laser printer controller and the print mechanism. The design also supports vertical page synchronization (top of page detection).

Abstract: A video controller includes a video block that connects to the print control engine and one laser driver. The video block includes a direct memory access (DMA) block, a video processor, a waveform generator including pattern and multiple pulse mode modulation, a frequency synthesizer, configuration registers, and a data bus. The frequency synthesizer connects to the waveform generator. The configuration registers connect to the DMA block, video processor and the waveform generator. The data bus, operative to carry bus control signals, connects the DMA block, video processor, waveform generator, and the configuration registers.

Abstract: A digital circuit generates very precise varying clock frequencies for applications that can tolerate a small degree of jitter but require exact longer term frequencies, e.g. a video clock for a laser printer. Some subpixel jitter is acceptable, but the overall pixel rate remains exact and consistent. In some applications, the jitter may be desirable to smear the EMI spectrum. For example, if the high frequency input clock is modulated, the edges of the video clock will also be modulated yet remain within the jitter and frequency specification.

Abstract: Embodiments of the present invention are described in an integrated circuit. The integrated circuit comprises circuit elements configured to be clocked via an oscillating signal, and a detector. The detector is configured to detect a state of the oscillating signal and provide a detection signal indicative of the state of the oscillating signal. The detector comprises a first delay line configured to provide a first delayed signal to logic that provides the detection signal.

Abstract: A digital circuit generates very precise varying clock frequencies for applications that can tolerate a small degree of jitter but require exact longer term frequencies, e.g. a video clock for a laser printer. Some subpixel jitter is acceptable, but the overall pixel rate remains exact and consistent. In some applications, the jitter may be desirable to smear the EMI spectrum. For example, if the high frequency input clock is modulated, the edges of the video clock will also be modulated yet remain within the jitter and frequency specification.

Abstract: Embodiments of the present invention are described in an integrated circuit. The integrated circuit comprises circuit elements configured to be clocked via an oscillating signal, and a detector. The detector is configured to detect a state of the oscillating signal and provide a detection signal indicative of the state of the oscillating signal. The detector comprises a first delay line configured to provide a first delayed signal to logic that provides the detection signal.