Abstract: A two-point phase modulator comprising a phase locked loop, PLL, having a voltage controlled oscillator, VCO, and a feedback path, a first modulation circuit for introducing a first modulation signal into the feedback path, the first modulation circuit generating the first modulation signal using a reference clock signal extracted from the PLL and derived from a first clock, a second modulation circuit for introducing a second modulation input into the VCO, the second modulation circuit generating the second modulation signal using a clock signal generated independently of the reference clock and a synchronizer for aligning the second modulation signal in time with the first clock signal.

Abstract: A two-point phase modulator comprising a phase locked loop, PLL, having a voltage controlled oscillator, VCO, and a feedback path, a first modulation circuit for introducing a first modulation signal into the feedback path, the first modulation circuit generating the first modulation signal using a reference clock signal extracted from the PLL and derived from a first clock, a second modulation circuit for introducing a second modulation input into the VCO, the second modulation circuit generating the second modulation signal using a clock signal generated independently of the reference clock and a synchronizer for aligning the second modulation signal in time with the first clock signal.

Abstract: A method of reducing d.c. offset comprises comparing the a first variable signal with a second variable signal, producing a control signal in dependence upon the comparison, providing the control signal to a charge pump for generation of a feedback signal, and varying the first signal and/or the second signal in dependence upon the feedback signal thereby reducing any difference between the d.c. level of the first signal and the d.c. level of the second signal.

Abstract: A frequency generation circuit comprises a crystal oscillator (10) for providing an input frequency, a phase-locked loop circuit (28), and a programmable frequency divider (42) for frequency dividing an output from the phase-locked loop circuit. The frequency generation circuit can generate a plurality of different output frequencies for supply to respective DAB and FM tuners (50, 60, 70). The frequency generation circuit can be used, together with a baseband circuit (14), in a radio receiver (1, 2). The same oscillator (10) and phase-locked loop circuit are used to drive the baseband circuit.

Abstract: A method of reducing d.c. offset comprises comparing the a first variable signal with a second variable signal, producing a control signal in dependence upon the comparison, providing the control signal to a charge pump for generation of a feedback signal, and varying the first signal and/or the second signal in dependence upon the feedback signal thereby reducing any difference between the d.c. level of the first signal and the d.c. level of the second signal.

Abstract: A digital tuner has an input tuning range with lower and upper limit frequencies. An up converter converts an input signal to an intermediate frequency signal whose frequency is higher than the upper frequency limit of the input range. A downconverter is a zero intermediate frequency quadrature converter which converts the intermediate frequency signal to in-phase and quadrature baseband signals. The upconverter has a local oscillator fundamental frequency which is greater than the upper frequency limit of the input tuning range.

Abstract: A digital tuner has an input tuning range with lower and upper limit frequencies. An up converter converts an input signal to an intermediate frequency signal whose frequency is higher than the upper frequency limit of the input range. A downconverter is a zero intermediate frequency quadrature converter which converts the intermediate frequency signal to in-phase and quadrature baseband signals. The upconverter has a local oscillator fundamental frequency which is greater than the upper frequency limit of the input tuning range.

Abstract: A tuner for digital terrestrial television has an input section which supplies a sampled intermediate signal, for example at zero intermediate frequency and digitised by an ADC, corresponding to a desired reception channel corrupted by interference such as impulsive noise interference. A threshold generator generates a threshold which is larger than a moving average of the amplitudes of consecutive samples and a comparator compares the amplitudes of the samples with the threshold. If a sample amplitude exceeds the threshold, a corrector sets to zero the sample before processing by a fast Fourier transform. The threshold generator excludes samples which have been set to zero from the moving average.