Abstract: Techniques for scheduling merged store operations are described. In an embodiment, an apparatus includes a data cache; a fill buffer; a store buffer to store first information associated with a first retired store operation and second information associated with a second retired store operation; a store coalescing buffer (SCB) to receive the first information from the store buffer, to store the first information in an SCB entry, to merge the second information from the store buffer into the entry, and to provide data associated with the entry for a write to the data cache or the fill buffer; and a global store scheduler (GSS) to schedule the write relative to an other write from an other SCB in compliance with one or more store ordering rules.

Abstract: Techniques for a processor, method, and system to implement a chunky partial load to store forwarding for pipelined loads. A chunky partial logic identifies overlap of partial load to store forwarding in a load pipeline for a load, decomposes the load into chunks of uniform size for issuance of each chunk as a separate chunky load and schedules the issuance of the chunks. A chunky partial register receives and stores the chunks decomposed into the chunks and issues the chunks separately into the load pipeline as a load operation.

Abstract: Techniques and mechanisms for a processor speculatively execute two load instructions. In an embodiment, a first load instruction and a second instruction are to be executed in parallel with each other by a processor core. A first address operand of the first load instruction identifies a first register, and a second address operand of the second load instruction identifies a second register. A value in the second register is to be calculated based on a load from a memory location which is identified by the value of the first register. Predicted values of the first register and the second register are provided to enable the first load instruction and the second load instruction to be speculatively calculated concurrently with each other. In another embodiment, a verified register value is evaluated, based on a corresponding predicted value, to determine whether a speculative execution is to be interrupted or prevented.

Abstract: Techniques for misaligned memory to accesses an address-sliced cache are described. In an embodiment, an apparatus includes a data cache; and a memory execution unit to access the data cache, the memory execution unit including multiple slice portions, wherein each slice portion is to perform memory access operations for a corresponding address range, and wherein a first slice portion includes low-split circuitry to perform a one or more low-split operations for a low-order portion of a data value and a second slice portion includes high-split circuitry to perform one or more high-split operations for a high-order portion of the data value.

Abstract: Embodiments of a processor for MAD training comprise: decode circuitry to decode instructions into uops, including a plurality of load and store uops; memory execution circuitry executes the plurality of load uops to load data from a memory subsystem and to execute the plurality of store uops to store data to the memory subsystem; and memory alias disambiguation (MAD) prediction circuitry to make a prediction as to whether a first load uop of the plurality of load uops can be executed prior to execution of a first one or more store uops of the plurality of store uops without causing a conflict, the MAD circuitry to make the prediction based on first prediction circuitry when a first confidence value indicated by the first prediction circuitry is above a threshold and to make the prediction based on second prediction circuitry when the first confidence value is at or below the threshold.

Abstract: An apparatus and method for efficiently executing wide vector load instructions. For example, one example method comprises: fetching a vector load instruction having one or more fields to indicate data to be loaded having a width greater than a data pipe width of a cache subsystem; allocating multiple data pipes of the cache subsystem to concurrently provide multiple corresponding portions of the data, wherein the multiple data pipes are to be allocated from multiple slices of the plurality of slices or from a single slice of the plurality of slices; aligning the multiple corresponding portions of the data within a register or other memory having a size greater than or equal to the width of the data; and providing the data to execution circuitry over an interconnect having a width greater than or equal to the width of the aligned data.

Abstract: An apparatus and method for predicting a page address. For example, one embodiment of a processor comprises: decode circuitry to decode a memory access instruction; execution circuitry to execute the memory access instruction to perform a corresponding memory access operation, the execution circuitry comprising: prediction circuitry to predict a physical address or portion thereof corresponding to the memory access operation based on an instruction pointer (IP) value associated with the memory access instruction; identifying a data cache tag value using the physical address or portion thereof; and accessing a corresponding cache line of a data cache responsive to validating the data cache tag value and the physical address or portion thereof.

Abstract: In one embodiment, a method includes: receiving, in a prediction circuit associated with a cache memory of a processor, a load operation to load information stored in a memory; accessing at least one prediction structure of the prediction circuit to obtain prediction information associated with the load operation, the prediction information comprising a predicted virtual address for the load operation; and dispatching the load operation to a load pipeline of the processor using the predicted virtual address for the load operation. Other embodiments are described and claimed.

Abstract: Techniques for slicing memory of a hardware processor core by linear address are described.

Abstract: An apparatus and method for implementing a Level 0 cache within a cache subsystem. For example, one embodiment of a processor comprises: a cache subsystem comprising a Level-0 cache; a scheduler to schedule a load operation indicating data to be loaded; and a load hit predictor to predict whether the data indicated by the load operation is stored in the LO cache and to generate a wakeup signal to the scheduler in response to predicting that the data is stored in the LO cache. Some implementations perform store forwarding in response to load operations using a multi-step approach in which a partial linear address check is performed to determine load operations which are eligible for store forwarding. A full address check is performed for those load operations which are eligible in which the address of the load is compared against the address of a youngest older store operation.

Abstract: Techniques for slicing memory of a hardware processor core by linear address are described.

Abstract: Techniques for prefetching by a hardware processor are described. In certain examples, a hardware processor includes execution circuitry, cache memories, and prefetcher circuitry. The execution circuitry is to execute instructions to access data at a memory address. The cache memories include a first cache memory at a first cache level and a second cache memory at a second cache level. The prefetcher circuitry is to prefetch the data from a system memory to at least one of the plurality of cache memories, and it includes a first-level prefetcher to prefetch the data to the first cache memory, a second-level prefetcher to prefetch the data to the second cache memory, and a plurality of prefetch filters. One of the prefetch filters is to filter exclusively for the first-level prefetcher. Another of the prefetch filters is to maintain a history of demand and prefetch accesses to pages in the system memory and to use the history to provide training information to the second-level prefetcher.

Abstract: Techniques for scheduling merged store operations are described. In an embodiment, an apparatus includes a data cache; a fill buffer; a store buffer to store first information associated with a first retired store operation and second information associated with a second retired store operation; a store coalescing buffer (SCB) to receive the first information from the store buffer, to store the first information in an SCB entry, to merge the second information from the store buffer into the entry, and to provide data associated with the entry for a write to the data cache or the fill buffer; and a global store scheduler (GSS) to schedule the write relative to an other write from an other SCB in compliance with one or more store ordering rules.

Abstract: A processor and method are described for a multi-level reservation station.

Abstract: An apparatus and method for early page address prediction. For example, one embodiment of a processor comprises: an instruction fetch circuit to fetch a load instruction; a decoder to decode the load instruction; execution circuitry to execute the load instruction to perform a load operation, the execution circuitry including an address generation unit (AGU) to generate an effective address to be used for the load operation; and early page prediction (EPP) circuitry to use one or more attributes associated with the load instruction to predict a physical page address for the load instruction simultaneously with the AGU generating the effective address and/or prior to generation of the effective address.

Abstract: A processor includes a store buffer to store store instructions to be processed to store data in main memory, a load buffer to store load instructions to be processed to load data from main memory, and a loop invariant code motion (LICM) protection structure coupled to the store buffer and the load buffer. The LPT tracks information to compare an address of a store or snoop microoperation with entries in the LICM and re-loads a load microoperation of a matching entry.

Abstract: A processor and method are described for a multi-level reservation station.

Abstract: A processor includes a set of execution units in an out-of-order execution pipeline, and a hardware profiler in the out-of-order execution pipeline coupled to the set of execution units and to profile instructions executed by the set of execution units, the hardware profiler to generate a profiling interrupt, the profiling interrupt to initiate an optimization of a basic block of instructions in response to determining that a whitelist bit is set corresponding to the basic block of instructions, the whitelist bit to identify the basic block of instructions for immediate optimization.

Abstract: A processor includes a store buffer to store store instructions to be processed to store data in main memory, a load buffer to store load instructions to be processed to load data from main memory, and a loop invariant code motion (LICM) protection structure coupled to the store buffer and the load buffer. The LPT tracks information to compare an address of a store or snoop microoperation with entries in the LICM and re-loads a load microoperation of a matching entry.

Abstract: An apparatus and method for early page address prediction. For example, one embodiment of a processor comprises: an instruction fetch circuit to fetch a load instruction; a decoder to decode the load instruction; execution circuitry to execute the load instruction to perform a load operation, the execution circuitry including an address generation unit (AGU) to generate an effective address to be used for the load operation; and early page prediction (EPP) circuitry to use one or more attributes associated with the load instruction to predict a physical page address for the load instruction simultaneously with the AGU generating the effective address and/or prior to generation of the effective address.