Abstract: A method is described for facilitating use of a first pattern utilizing XOR data formatting in an electronic tester. The method includes dividing the first pattern into at least a first group and a second group, the tester to successively execute the first group and the second group. The method further includes assuming an entry state for each group is one of two binary conditions and inverting programmed commands for the second group if an ending state of the first group is not equal to the assumed entry state.

Abstract: An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns.

Abstract: An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns.

Abstract: A method of connecting one or more testing devices to ports of a DUT through a switching network, to execute a testing procedure includes generating a switching network map defining connections within the switching network to implement electrical paths through the switching network. Each of the electrical paths is representative of a connection of one of the testing devices to one of the I/O ports of the DUT. The method further includes receiving commands that uniquely specify an electrical path connecting a particular testing device to a particular I/O port of the DUT. The method compares each command to the switching network map to identify a corresponding electrical path through the switching network, and implements that path associated the command through the network. The method further includes sequentially implementing the electrical paths corresponding to the one or more commands in a predetermined order.

Abstract: An apparatus to receive a response signal sent from a device under test. The apparatus includes pin electronics to identify a response signal contained in a composite signal. The composite signal is a composite, or sum, of the response signal and a test signal. The pin electronics has a driver to send the test signal to the device under test, and a receiver to receive the composite signal and to separate the response signal from the composite signal.

Abstract: An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patters to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns.

Abstract: An apparatus to receive a response signal sent from a device under test. The apparatus includes pin electronics to identify a response signal contained in a composite signal. The composite signal is a composite, or sum, of the response signal and a test signal. The pin electronics has a driver to send the test signal to the device under test, and a receiver to receive the composite signal and to separate the response signal from the composite signal.

Abstract: A method is described that decompresses at least a section of a first test pattern within a first decompression engine while simultaneously decompressing at least a section of a second test pattern within a second decompression engine. The first test pattern is to be applied to a first device under test (DUT) connection. The second test pattern is to be applied to a second DUT connection.

Abstract: An automated test system that has analog and digital resources for testing mixed signal ICs. A control pattern is provided that is used by the automated test system to simultaneously control both the digital resources and the analog resources. The control pattern is comprised of a sequentially executed two-dimensional array with columns corresponding to analog and digital resources. The automated test system uses the control pattern to control both the analog and digital resources.

Abstract: A method of connecting one or more testing devices to ports of a DUT through a switching network, to execute a testing procedure includes generating a switching network map defining connections within the switching network to implement electrical paths through the switching network. Each of the electrical paths is representative of a connection of one of the testing devices to one of the I/O ports of the DUT. The method further includes receiving commands that uniquely specify an electrical path connecting a particular testing device to a particular I/O port of the DUT. The method compares each command to the switching network map to identify a corresponding electrical path through the switching network, and implements that path associated the command through the network. The method further includes sequentially implementing the electrical paths corresponding to the one or more commands in a predetermined order.

Abstract: An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns.