Abstract: A semiconductor device and fabrication method are described for integrating stacked top and bottom nanosheet transistors by providing a nanosheet transistor stack having bottom and top Si/SiGe superlattice structures (11-14, 17-20) which are separated from one another by a barrier oxide layer (15) and which are separately processed to form bottom gate electrodes having a first gate structure (40A-B) in the bottom Si/SiGe superlattice structures and to form top gate electrodes having a second, different gate structure (46A-B) in the top Si/SiGe superlattice structures.

Abstract: A nanosheet semiconductor device and fabrication method are described for integrating the fabrication of nanosheet transistors (71) and capacitors/sensors (72) in a single nanosheet process flow by forming separate transistor and capacitor/sensor stacks (12A-16A, 12B-16B) which are selectively processed to form gate electrode structures (68A-C) which replace remnant SiGe sandwich layers in the transistor stack, to form silicon fixed electrodes using silicon nanosheets (13C, 15C) on a first side of the capacitor/sensor stack, and to form SiGe fixed electrodes using SiGe nanosheets (12C, 14C, 16C) from the middle of remnant SiGe sandwich layers in the capacitor/sensor stack (e.g., 16-2) which are separated from the silicon fixed electrodes by selectively removing top and bottom SiGe nanosheets (e.g., 16-1, 16-3) from the remnant SiGe sandwich layers in the capacitor/sensor stack.

Abstract: A semiconductor device and fabrication method are described for forming a nanosheet transistor device by forming a nanosheet transistor stack (12-18, 25) of alternating Si and SiGe layers which are selectively processed to form metal-containing current terminal or source/drain regions (27, 28) and to form control terminal electrodes (36A-D) which replace the SiGe layers in the nanosheet transistor stack and are positioned between the Si layers which form transistor channel regions in the nanosheet transistor stack to connect the metal source/drain regions, thereby forming a nanosheet transistor device.

Abstract: A nanosheet MEMS sensor device and method are described for integrating the fabrication of nanosheet transistors (61) and MEMS sensors (62) in a single nanosheet process flow by forming separate nanosheet transistor and MEMS sensor stacks (12A-16A, 12B-16B) of alternating Si and SiGe layers which are selectively processed to form gate electrodes (49A-C) which replace the silicon germanium layers in the nanosheet transistor stack, to form silicon fixed electrodes using silicon layers (13B-2, 15B-2) on a first side of the MEMS sensor stack, and to form silicon cantilever electrodes using silicon layers (13B-1, 15B-1) on a second side of the MEMS sensor stack by forming a narrow trench opening (54) in the MEMS sensor stack to expose and remove remnant silicon germanium layers on the second side in the MEMS sensor stack.

Abstract: A circuit includes a P-channel transistor formed in a P-well and an N-channel transistor formed in an N-well. The first P-channel transistor has a control electrode connected to the P-well. The N-channel transistor is coupled in series with the P-channel transistor and has a control electrode connected to the N-well. Connecting the control electrodes of the P-channel and N-channel transistors to respective P-well and N-well effectively reduces crowbar current in the circuit.

Abstract: A semiconductor device and fabrication method are described for integrating a nanosheet transistor with a capacitor or nonvolatile memory cell in a single nanosheet process flow by forming a nanosheet transistor stack (11-18) of alternating Si and SiGe layers which are selectively processed to form epitaxial source/drain regions (25A, 25B) and to form gate electrodes (33A-D) which replace the silicon germanium layers in the nanosheet transistor stack, and then selectively forming one or more insulated conductive electrode layers (e.g., 37/39, 25/55, 64/69) adjacent to the nanosheet transistor to define a capacitor or nonvolatile memory cell that is integrated with the nanosheet transistor.

Abstract: A nanosheet semiconductor device and fabrication method are described for integrating the fabrication of nanosheet transistors (71) and capacitors/sensors (72) in a single nanosheet process flow by forming separate transistor and capacitor/sensor stacks (12A-16A, 12B-16B) which are selectively processed to form gate electrode structures (68A-C) which replace remnant SiGe sandwich layers in the transistor stack, to form silicon fixed electrodes using silicon nanosheets (13C, 15C) on a first side of the capacitor/sensor stack, and to form SiGe fixed electrodes using SiGe nanosheets (12C, 14C, 16C) from the middle of remnant SiGe sandwich layers in the capacitor/sensor stack (e.g., 16-2) which are separated from the silicon fixed electrodes by selectively removing top and bottom SiGe nanosheets (e.g., 16-1, 16-3) from the remnant SiGe sandwich layers in the capacitor/sensor stack.

Abstract: A semiconductor device and fabrication method are described for integrating stacked top and bottom nanosheet transistors by providing a nanosheet transistor stack having bottom and top Si/SiGe superlattice structures (11-14, 17-20) which are separated from one another by a barrier oxide layer (15) and which are separately processed to form bottom gate electrodes having a first gate structure (40A-B) in the bottom Si/SiGe superlattice structures and to form top gate electrodes having a second, different gate structure (46A-B) in the top Si/SiGe superlattice structures.

Abstract: A semiconductor device and fabrication method are described for integrating stacked top and bottom nanosheet transistors by providing a nanosheet transistor stack having bottom and top Si/SiGe superlattice structures (11-14, 17-20) which are separated from one another by a barrier oxide layer (15) and which are separately processed to form first remnant silicon germanium nanosheet layers (12, 14) in the bottom Si/SiGe superlattice structures having a first gate length dimension (DG1) and to form second remnant silicon germanium nanosheet layers (18, 20) in the top Si/SiGe superlattice structures having a second, smaller gate length dimension (DG2) so that the nanosheet transistor stack may then be processed to simultaneously form bottom and top gate electrodes which replace, respectively, the first and second remnant silicon germanium nanosheet layers.

Abstract: A semiconductor device and fabrication method are described for integrating a nanosheet transistor with a capacitor or nonvolatile memory cell in a single nanosheet process flow by forming a nanosheet transistor stack (11-18) of alternating Si and SiGe layers which are selectively processed to form epitaxial source/drain regions (25A, 25B) and to form gate electrodes (33A-D) which replace the silicon germanium layers in the nanosheet transistor stack, and then selectively forming one or more insulated conductive electrode layers (e.g., 37/39, 25/55, 64/69) adjacent to the nanosheet transistor to define a capacitor or nonvolatile memory cell that is integrated with the nanosheet transistor.

Abstract: A nanosheet MEMS sensor device and method are described for integrating the fabrication of nanosheet transistors (61) and MEMS sensors (62) in a single nanosheet process flow by forming separate nanosheet transistor and MEMS sensor stacks (12A-16A, 12B-16B) of alternating Si and SiGe layers which are selectively processed to form gate electrodes (49A-C) which replace the silicon germanium layers in the nanosheet transistor stack, to form silicon fixed electrodes using silicon layers (13B-2, 15B-2) on a first side of the MEMS sensor stack, and to form silicon cantilever electrodes using silicon layers (13B-1, 15B-1) on a second side of the MEMS sensor stack by forming a narrow trench opening (54) in the MEMS sensor stack to expose and remove remnant silicon germanium layers on the second side in the MEMS sensor stack.

Abstract: A semiconductor apparatus includes a first device cell and a second device cell. The first device cell includes a first active region including a first set of device fins, an insulator layer disposed over the first set of device fins, a first gate fin over the first set of fins, and a first edge fin disposed over a first edge of the first active region. The second device cell is adjacent the first device cell and includes a second active region including a second set of device fins, the insulator layer disposed over the second set of device fins, a second gate fin over the second set of device fins, and a second edge fin disposed over a second edge of the second active region. The first edge fin and the second edge fin are connected to a power rail, a ground rail, or to each other to define a capacitor between the first device cell and the second device cell.

Abstract: A circuit includes a P-channel transistor formed in a P-well and an N-channel transistor formed in an N-well. The first P-channel transistor has a control electrode connected to the P-well. The N-channel transistor is coupled in series with the P-channel transistor and has a control electrode connected to the N-well. Connecting the control electrodes of the P-channel and N-channel transistors to respective P-well and N-well effectively reduces crowbar current in the circuit.

Abstract: A package to die connection system and method are provided. The system includes a semiconductor device having a substrate with a top surface. A gasket is affixed to the top surface of the substrate and has at least one cavity with a portion of the cavity open to a sidewall of the gasket. A semiconductor die is attached to the top surface of the substrate. A sidewall of the semiconductor die is abutted with the sidewall of the gasket. A portion of a metal layer is exposed to the open portion of the cavity. A pillar located in the cavity is electrically connected to the exposed portion of the metal layer.

Abstract: An integrated circuit (IC) system includes a substrate, a first doped well of a first polarity in the substrate, a first electrode in contact with the doped well, a buried oxide (BOX) in contact with the doped well in the substrate, a first IC device including a second electrode formed on the BOX, and fuse control circuitry coupled to the first electrode and the second electrode. The fuse control circuitry is configured to cause voltages to be applied to the first and second electrodes to change a resistance level of the BOX in the vicinity of the second electrode.

Abstract: An integrated circuit (IC) system includes a substrate, a first doped well of a first polarity in the substrate, a first electrode in contact with the doped well, a buried oxide (BOX) in contact with the doped well in the substrate, a first IC device including a second electrode formed on the BOX, and fuse control circuitry coupled to the first electrode and the second electrode. The fuse control circuitry is configured to cause voltages to be applied to the first and second electrodes to change a resistance level of the BOX in the vicinity of the second electrode.