Abstract: A method of forming a semiconductor structure includes providing a substrate comprising a first material portion and a single crystal silicon layer on the first material portion. The substrate further comprises a major front surface, a major backside surface opposing the major front surface, and a plurality of grooves positioned in the major front surface. A buffer layer is deposited in one or more of the plurality of grooves. A semiconductor material is epitaxially grown over the buffer layer and in the one or more plurality of grooves, the epitaxially grown semiconductor material comprising a hexagonal crystalline phase layer and a cubic crystalline phase structure disposed over the hexagonal crystalline phase.

Abstract: A method of forming a semiconductor structure includes providing a substrate comprising a first material portion and a single crystal silicon layer on the first material portion. The substrate further comprises a major front surface, a major backside surface opposing the major front surface, and a plurality of grooves positioned in the major front surface. A buffer layer is deposited in one or more of the plurality of grooves. A semiconductor material is epitaxially grown over the buffer layer and in the one or more plurality of grooves, the epitaxially grown semiconductor material comprising a hexagonal crystalline phase layer and a cubic crystalline phase structure disposed over the hexagonal crystalline phase.

Abstract: A transistor comprises a substrate comprising a Group III/V compound semiconductor material having a cubic crystalline phase structure positioned on a hexagonal crystalline phase layer having a first region and a second region, the cubic crystalline phase structure being positioned between the first region and the second region of the hexagonal crystalline phase layer. A source region and a drain region are both positioned in the Group III/V compound semiconductor material. A channel region is in the Group III/V compound semiconductor material. A gate is over the channel region. An optional backside contact can also be formed. A source contact and electrode are positioned to provide electrical contact to the source region. A drain contact and electrode are positioned to provide electrical contact to the drain region. Methods of forming transistors are also disclosed.

Abstract: A method of forming a semiconductor structure includes providing a substrate comprising a first material portion and a single crystal silicon layer on the first material portion. The substrate further comprises a major front surface, a major backside surface opposing the major front surface, and a plurality of grooves positioned in the major front surface. A buffer layer is deposited in one or more of the plurality of grooves. A semiconductor material is epitaxially grown over the buffer layer and in the one or more plurality of grooves, the epitaxially grown semiconductor material comprising a hexagonal crystalline phase layer and a cubic crystalline phase structure disposed over the hexagonal crystalline phase.

Abstract: Methods for separating a plurality of diamagnetic directed self-assembled diamagnetic components are provided. One method includes, for instance: contacting a release substrate to the plurality of diamagnetic components, the plurality of diamagnetic components including a non-diamagnetic component affixed to a diamagnetic portion by a first adhesive, and removing the release substrate, the non-diamagnetic component being affixed to a final substrate by a second adhesive and the release substrate being affixed to the diamagnetic portion by a third adhesive, and wherein the removing removes the diamagnetic portion and at least a portion of the first adhesive from the non-diamagnetic component.

Abstract: A method of forming a semiconductor structure includes providing a substrate comprising a first material portion and a single crystal silicon layer on the first material portion. The substrate further comprises a major front surface, a major backside surface opposing the major front surface, and a plurality of grooves positioned in the major front surface. A buffer layer is deposited in one or more of the plurality of grooves. A semiconductor material is epitaxially grown over the buffer layer and in the one or more plurality of grooves, the epitaxially grown semiconductor material comprising a hexagonal crystalline phase layer and a cubic crystalline phase structure disposed over the hexagonal crystalline phase.

Abstract: A transistor comprises a substrate comprising a Group III/V compound semiconductor material having a cubic crystalline phase structure positioned on a hexagonal crystalline phase layer having a first region and a second region, the cubic crystalline phase structure being positioned between the first region and the second region of the hexagonal crystalline phase layer. A source region and a drain region are both positioned in the Group III/V compound semiconductor material. A channel region is in the Group III/V compound semiconductor material. A gate is over the channel region. An optional backside contact can also be formed. A source contact and electrode are positioned to provide electrical contact to the source region. A drain contact and electrode are positioned to provide electrical contact to the drain region. Methods of forming transistors are also disclosed.

Abstract: Systems, and methods of use thereof, for assembling a plurality of diamagnetic components. The system including a first stage and a second stage, wherein each of the first stage and the second stage include a plurality of substages, the plurality of substages arranged in a checkerboard pattern, and a plurality of openings between the plurality of substages, wherein the plurality of the substages and the plurality of the openings of the first stage are complimentary to the plurality of the substages and the plurality of the openings of the second stage.

Abstract: Methods for binning, or sorting a plurality of components for directed self-assembly are provided. One method includes, for instance: providing a mapped wafer suspended in a mounting assembly; selecting at least one of the plurality of components for removal based on a set of parameters; moving at least one of an actuated impulse source and the mounting assembly to align the actuated impulse source and the at least one of the plurality of components; and removing the at least one of the plurality of components using the actuated impulse source, the removed at least one of the plurality of components falling into a bin below, the at least one of the plurality of components falling in any orientation.

Abstract: Methods for separating a plurality of diamagnetic directed self-assembled diamagnetic components are provided. One method includes, for instance: contacting a release substrate to the plurality of diamagnetic components, the plurality of diamagnetic components including a non-diamagnetic component affixed to a diamagnetic portion by a first adhesive, and removing the release substrate, the non-diamagnetic component being affixed to a final substrate by a second adhesive and the release substrate being affixed to the diamagnetic portion by a third adhesive, and wherein the removing removes the diamagnetic portion and at least a portion of the first adhesive from the non-diamagnetic component.

Abstract: A transistor comprises a substrate comprising a Group III/V compound semiconductor material having a cubic crystalline phase structure positioned on a hexagonal crystalline phase layer having a first region and a second region, the cubic crystalline phase structure being positioned between the first region and the second region of the hexagonal crystalline phase layer. A source region and a drain region are both positioned in the Group III/V compound semiconductor material. A channel region is in the Group III/V compound semiconductor material. A gate is over the channel region. An optional backside contact can also be formed. A source contact and electrode are positioned to provide electrical contact to the source region. A drain contact and electrode are positioned to provide electrical contact to the drain region. Methods of forming transistors are also disclosed.

Abstract: Methods of and systems for assembling a plurality of ferromagnetic components into a grid-array are provided. One method includes applying a vibratory force to a magnetic stage, the magnetic stage comprising a plurality of magnets and spacers arranged in an array; depositing a plurality of ferromagnetic components, each having a ferromagnetic strip, onto the magnetic stage, the vibratory force distributing the plurality of the ferromagnetic components substantially evenly across a surface of the magnetic stage, and wherein the vibratory force aligns at least one of the plurality of ferromagnetic components with a node of maximum magnetic field strength of the magnetic stage; and removing a set of the plurality of ferromagnetic components that are not in a node of maximum magnetic field strength through physical inversion of the magnetic stage.

Abstract: A transistor comprises a substrate comprising a Group III/V compound semiconductor material having a cubic crystalline phase structure positioned on a hexagonal crystalline phase layer having a first region and a second region, the cubic crystalline phase structure being positioned between the first region and the second region of the hexagonal crystalline phase layer. A source region and a drain region are both positioned in the Group III/V compound semiconductor material. A channel region is in the Group III/V compound semiconductor material. A gate is over the channel region. An optional backside contact can also be formed. A source contact and electrode are positioned to provide electrical contact to the source region. A drain contact and electrode are positioned to provide electrical contact to the drain region. Methods of forming transistors are also disclosed.

Abstract: A method of forming a semiconductor structure includes providing a substrate comprising a first material portion and a single crystal silicon layer on the first material portion. The substrate further comprises a major front surface, a major backside surface opposing the major front surface, and a plurality of grooves positioned in the major front surface. A buffer layer is deposited in one or more of the plurality of grooves. A semiconductor material is epitaxially grown over the buffer layer and in the one or more plurality of grooves, the epitaxially grown semiconductor material comprising a hexagonal crystalline phase layer and a cubic crystalline phase structure disposed over the hexagonal crystalline phase.