Patents by Inventor Mark Dydyk

Mark Dydyk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Wafer backside grinding with stress relief
    Patent number: 8222118
    Abstract: A method of relieving stress in a semiconductor wafer and providing a wafer backside surface finish capable of hiding cosmetic imperfections. Embodiments of the invention include creating a wafer backside surface which can be used for all dies on the semiconductor wafer intended for different product applications and be deposited with backside metallization (BSM) material. The method provides a rough texture on the wafer backside followed by isotropic etching of the wafer backside to recover the wafer strength as well as to preserve the rough texture of the wafer backside. After wafer backside metallization, the rough texture of the wafer backside hides cosmetic imperfections introduced by subsequent processes.
    Type: Grant
    Filed: December 15, 2008
    Date of Patent: July 17, 2012
    Assignee: Intel Corporation
    Inventors: Mark Dydyk, Arturo Urquiza, Charles Singleton, Tim McIntosh
  • Wafer cutting methods and packages using dice derived therefrom
    Patent number: 7795116
    Abstract: A wafer-cutting process includes first cutting a semiconductive wafer along a first path at a given first cutting intensity including cutting across an intersection. The process also includes second cutting the semiconductive wafer along a second path at a given second cutting intensity. The second cutting intensity is diminished during crossing the intersection and resumed to the given cutting intensity after crossing the intersection.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: September 14, 2010
    Assignee: Intel Corporation
    Inventors: Mark Dydyk, Erasenthiran Poonjolai
  • Wafer Backside Grinding with Stress Relief
    Publication number: 20100151678
    Abstract: A method of relieving stress in a semiconductor wafer and providing a wafer backside surface finish capable of hiding cosmetic imperfections. Embodiments of the invention include creating a wafer backside surface which can be used for all dies on the semiconductor wafer intended for different product applications and be deposited with backside metallization (BSM) material. The method provides a rough texture on the wafer backside followed by isotropic etching of the wafer backside to recover the wafer strength as well as to preserve the rough texture of the wafer backside. After wafer backside metallization, the rough texture of the wafer backside hides cosmetic imperfections introduced by subsequent processes.
    Type: Application
    Filed: December 15, 2008
    Publication date: June 17, 2010
    Inventors: Mark Dydyk, Arturo Urquiza, Charles Singleton, Tim McIntosh
  • Wafer cutting methods and packages using dice derived therefrom
    Publication number: 20100078768
    Abstract: A wafer-cutting process includes first cutting a semiconductive wafer along a first path at a given first cutting intensity including cutting across an intersection. The process also includes second cutting the semiconductive wafer along a second path at a given second cutting intensity. The second cutting intensity is diminished during crossing the intersection and resumed to the given cutting intensity after crossing the intersection.
    Type: Application
    Filed: September 29, 2008
    Publication date: April 1, 2010
    Inventors: Mark Dydyk, Erasenthiran Poonjolai