Abstract: In one embodiment, a method and apparatus for reading one block of a nonvolatile memory device while writing to another block of a nonvolatile memory device is disclosed.

Abstract: Sense path and write path architectures for read and write accesses of a memory device having memory cells that store n binary bits are disclosed. “By-output” architectures provide one output per bit such that each selected memory cell is mapped to n outputs and the n bits stored in the selected memory cell are read in parallel. “By-address” architectures provide one address per bit such that each selected memory cell is mapped to one output, and the n bits stored in the selected memory cell are read sequentially.

Abstract: A memory system having memory cells for storing one of a plurality of threshold levels to store more than a single bit per cell is disclosed. The memory system contains a switch control to permit selection of an operating mode including a multi-level cell mode and a standard cell mode. The memory system further includes a reading circuit to read a single bit per cell when operating in the standard cell mode, and to read multiple bits of data per memory cell when operating in the multi-level cell mode. A program circuit programs a single bit of data per memory cell for addressed memory cells when operating in the standard cell mode, and programs multiple bits of data per memory cell for addressed memory cells when operating in the multi-level cell mode.

Abstract: Methods and apparatus for determining the state of a memory cell having more than two possible states are disclosed. For a first embodiment, the state of a flash cell having n states, where n is a power of 2, is determined by selectively comparing the threshold voltage V.sub.t of a selected memory cell to (n-1) reference voltages. For every two states, a single comparator is provided such that the total number of comparators is equal to the number of bits stored in the memory cell.

Abstract: A method and circuitry are described that permit one to utilize a partially functional integrated circuit memory. A memory array is segregated into separate blocks that can each be isolated to minimize the amount of the memory array rendered unusable by a defect. Circuitry is also provided to program memory cells within the array to one of at least three amounts of charge and thereby increase the amount of storage provided by the remaining functional blocks.

Abstract: Sense path and write path architectures for read and write accesses of a memory device having memory cells that store n binary bits are disclosed. "By-output" architectures provide one output per bit such that each selected memory cell is mapped to n outputs and the n bits stored in the selected memory cell are read in parallel. "By-address" architectures provide one address per bit such that each selected memory cell is mapped to one output, and the n bits stored in the selected memory cell are read sequentially.

Abstract: Sense path and write path architectures for read and write accesses of a memory device having memory cells that store n binary bits are disclosed. "By-output" architectures provide one output per bit such that each selected memory cell is mapped to n outputs and the n bits stored in the selected memory cell are read in parallel. "By-address" architectures provide one address per bit such that each selected memory cell is mapped to one output, and the n bits stored in the selected memory cell are read sequentially.

Abstract: Sense path and write path architectures for read and write accesses of a memory device having memory cells that store n binary bits are disclosed. "By-output" architectures provide one output per bit such that each selected memory cell is mapped to n outputs and the n bits stored in the selected memory cell are read in parallel. "By-address" architectures provide one address per bit such that each selected memory cell is mapped to one output, and the n bits stored in the selected memory cell are read sequentially.

Abstract: A method and apparatus for correcting errors in a multilevel cell memory is described. A multilevel cell memory is comprised of multilevel cells, each capable of storing two or more bits of data. A plurality of data bits is received by the multilevel cell memory. The plurality of data bits are sorted into two or more data words. Error correction codes are generated for each of the two or more data words. A memory element bit pattern is formed that comprises one bit from each of the two or more data words. A charge state associated with the memory element bit pattern is stored in one of the multilevel cells.

Abstract: Methods and apparatus for determining the state of a memory cell having more than two possible states are disclosed. For a first embodiment, the state of a flash cell having n states, where n is a power of 2, is determined by selectively comparing the threshold voltage V.sub.t of a selected memory cell to (n-1) reference voltages. For every two states, a single comparator is provided such that the total number of comparators is equal to the number of bits stored in the memory cell.

Abstract: A nonvolatile memory includes a global line and a first block and a second block. The first block includes a plurality of first local lines and a first local decoder coupled to the global line and the first local lines for selectively coupling the global line to one of the first local lines in accordance with an address when the first local decoder is enabled and for isolating the first local lines from the global line when the first local decoder is disabled. The second block includes a plurality of second local lines and a second local decoder coupled to the global line and the second local lines for selectively coupling the global line to one of the second local lines in accordance with the address when the second local decoder is enabled and for isolating the second local lines from the global line when the second local decoder is disabled such that interference between the first and second blocks is eliminated during memory operations.

Abstract: Schemes for verifying the successful programming of a memory cell having more than two possible states are disclosed. Each program verify reference flash cell is set to have a V.sub.t that defines a boundary of a possible state for the selected flash cell. For a first embodiment, program verify reference flash cells are used in the place of read reference cells to perform a binary search read operation similar to a standard read operation for the memory device architecture. The data sensed by the write verify operation is compared to expected data. For a second embodiment, a single program verify reference flash cell is used to define a threshold voltage beyond which the floating gate of the selected flash cell must be programmed to pass the write verify operation. Thus, for the second embodiment, the program verify reference flash cell is used to verify the analog V.sub.

Abstract: A method and circuitry for providing dual row selection using a multiplexed tri-level decoder is disclosed. For one embodiment, the multiplexed tri-level decoder is a 3:8 decoder, the major components of which are a buffer and 8 three input NAND circuits. The NAND circuits are peculiar in that the inputs are referenced to a VCC operational voltage supply, and the outputs are referenced to a VPX tri-level supply voltage. The output of each NAND circuit is used to select one row or word line. During preconditioning and post conditioning, the decoder is required to enable two adjacent rows: the row selected and the next row. The present design implements dual row selection by adding a pass transistor that connects the word line enable driver to the driver of the previous row within the VPX level circuitry. This is in contrast to the previous design approach of implementing dual row selection by using VCC level logic. The disclosed implementation eliminates gates in the speed path of the circuit.

Abstract: A method and apparatus for sensing the state of floating gate memory cells in a memory array. Because of its stability and accuracy, the sensing apparatus may be used for sensing the state of multi-bit floating gate memory cells. The state of a memory cell is sensed by applying a variable gate voltage to the top gate of the floating gate memory cell and comparing the cell current to a fixed reference current. A circuit detects when the cell current is equal to the reference current. When the currents are equal, the value of the variable gate voltage indicates the state of the memory cell. For one embodiment, an analog-to-digital converter converts the variable gate voltage to a digital value that is latched when the currents are equal. The latched digital value indicates the state of the memory cell. For this embodiment, a ramp voltage or other suitable variable voltage may be used as the variable gate voltage.

Abstract: Sense path and write path architectures for read and write accesses of a memory device having memory cells that store n binary bits are disclosed. "By-output" architectures provide one output per bit such that each selected memory cell is mapped to n outputs and the n bits stored in the selected memory cell are read in parallel. "By-address" architectures provide one address per bit such that each selected memory cell is mapped to one output, and the n bits stored in the selected memory cell are read sequentially.

Abstract: A memory device is disclosed which includes memory cells having m possible states, where m is at least 2. The memory device includes a multiplexed pair of output paths, wherein each output path is coupled to sense the state of a memory cell and includes a read path circuit, a column load circuit, and a comparator. Provided between the pair of output paths is a switching circuit for coupling the comparators to one another in response to a control signal. For single-bit read operations, each output path senses and outputs the data of the associated memory cell, and the control signal is inactive. When the control signal is active, the read path circuit and column load circuit of one of the output paths is disabled and the switching circuit couples the other read path circuit to the second comparator such that the state of the memory cell is sensed by two comparators.

Abstract: A nonvolatile memory includes a first and a second output, a main array having a first and a second column, and a redundant array having a first and a second redundant column. A logic includes a first and a second CAM set. The first CAM set activates the first redundant column to replace the first column if defective. The second CAM set activates the second redundant column to replace the second column if it is defective. A configuration circuit is provided for controlling the logic to selectively couple the first and second columns and the first and second redundant columns to the first and second outputs. When the configuration circuit is in a first state, the logic couples the first redundant column to the first output if it is activated and the second redundant column to the second output if it is activated.

Abstract: A sense amplifier for sensing the impedance between two terminals includes an amplification stage whose input is connected to one of the terminals. The input is connected to a power supply voltage VCC through two transistors in parallel. One transistor provides a high speed by providing a large current when the voltage on the input is low. Moreover, to increase speed and save power, that transistor turns off when the amplification stage input voltage is slightly above the amplification stage trip voltage. The other transistor provides a small current to pull the amplification stage input up almost to VCC to reduce the amplification stage power consumption. The small current does not interfere significantly with the pull-down speed. One of the amplification stage power terminals is connected to ground through current limiting transistors to reduce the amplification stage power consumption when the amplification stage input voltage is at its low value which is slightly below the trip voltage.

Abstract: In a memory array in which logic signals of a first and a second voltage levels are used for selecting memory positions in the array for read operations and at least one signal of a voltage level higher than the first and second voltage levels may appear, and including a plurality of wordlines each joined to a common node by individual row decoders, a predecoder circuit for selecting a plurality of wordlines from which a row decoder may select an individual wordline including a full CMOS NAND gate arranged to provide output voltage levels of the first and a second voltage levels, a plurality of weak P channel devices each connected to one of the wordlines, means for operating the weak P channel devices to provide voltage levels of the higher level and below at the wordlines, means for limiting value of voltage transferred to the common point to be less than the higher voltage level, and means for limiting the level of the voltage transferred to the common node from the NAND gate to be less than a predetermine