Abstract: An in-line decryptor is employed to decrypt software (program instructions) transferred from a read only memory to a central processing unit. The in-line decryptor comprises a keystream generator that contains a cryptographic algorithm coupled to a memory that stores cryptographic keys. A combining function implemented using two substitution functions and two XOR functions generates an output keystream of the keystream generator. The decryptor uses the cryptographic algorithm to initialize a variation of a one time pad cryptosystem. Using a number of relatively short pseudorandom sequences and a simple combining function, a much longer address-dependent pseudorandom sequence is created. This sequence is used to decrypt the encrypted software in real time on an instruction-by-instruction basis.

Abstract: A system and method that provides an electronic indication that unauthorized access has been gained to a system. The mechanisms used by the present invention cannot be forged, bypassed, or subverted. In fact, even persons authorized to access the environment cannot do so without leaving evidence. When an intrusion is detected, a random number is generated. This random number, referred to as an audit count, is then encrypted and stored, and a sequence number is incremented. To recover this information at a later time, a trusted individual inserts an external device containing a decryption key. The decryption key is extracted, and the encrypted audit count and sequence number are decrypted and displayed. Periodic verification that the audit count and sequence number have not changed provides assurance that access has not been gained to the system.

Abstract: A system for remotely controlling a desired door locking or other function in a vehicle or other protected environment has a transmitter and receiver for communicating a message including a sequence number, the code of a selected function to be performed and an authenticator. An algorithm in the transmitter and in the receiver has a cryptographic key and a seed code. Each algorithm generates the authenticator as a function of both the seed code and the function code; if the authenticators are equal, the message is valid. Upon each transmission the seed code is updated and the sequence number is incremented. The receiver updates its seed code according to the transmitted sequence number to keep the algorithms in synchronism.

Abstract: Disclosed is a method and apparatus for securely conveying network control data across a cryptographic boundary (12). A plain text (PT) processor (32) located on a plain text side (14) of the cryptographic boundary (12) transfers unencrypted data packets to and from plain text devices on the plain text side (14). A crypto processor (34) encrypts the unencrypted data packets from the PT processor (32). A cipher text (CT) processor (20) transfers encrypted data packets from the crypto processor (34) to network devices located on a cipher text side (16) of the cryptographic boundary (12). The CT processor (20) transfers the encrypted data packets to the appropriate destination address by reading the destination address from an isolated RAM (22) containing a mapping table (26) which is automatically constructed upon initialization by the CT processor (20).

Abstract: A general purpose, high-speed encryption system and method, based on a linear feedback shift register (LFSR) that provides inputs to one or more mathematically independent nonlinear output functions, resulting in the generation of multiple keystream outputs per clock cycle. Due to the parallel architecture, the system need only operate at a rate of 1/N, where N is the number of output functions. For example, the system can encrypt an 8-bit byte in one-eighth the time required for a conventional bit-oriented stream cipher. Alternatively, with high-speed serial-to-parallel and parallel-to-serial interface converters, the system can encrypt a serial data stream at a rate N times that of the system itself.

Abstract: A set/scan test capability is provided for a circuit that includes sensitive subcircuits, but that can be latched out to prevent reverse engineering the sensitive elements. A mechanism to inhibit set/scan test access to at least some of the sensitive subcircuits is selectively actuated by a control circuit to override a normal set/scan test and inhibit set/scan access to the sensitive subcircuits. Various implementations are possible, such as fusible-link PROMs for irreversibly inhibiting set/scan access to the sensitive subcircuits after an initial non-inhibited test period, the use of encryption codes to enable repeated set/scan access to the sensitive subcircuits, and an erasable/reprogrammable mechanism for inhibiting set/scan access to programmed sets of subcircuits.

Abstract: An encryption system and method based on the mathematics of Chaos theory, which provides protection of data from unauthorized modification and use during its storage and transmission. At its core are nonlinear equations which exhibits random, noise-like properties, given certain parameter values. When iterated, a periodic sequence is produced with an extremely long cycle length. A domain transformation process is then used to convert the floating-point iterates into binary form for summation with the digital data to be protected. The result is an encrypted message that cannot be modified, replaced, or understood by anyone other than the intended party. The use of Chaos theory in combination with the domain transformation process results in an easily implemented cryptographic system with extremely robust cryptographic properties. The concepts of the present invention also lend themselves well to either hardware or software implementations.