Abstract: A circuit element of a multi-dimensional dynamic adaptive neural network array (DANNA) may comprise a neuron/synapse select input functional to select the circuit element to function as one of a neuron and a synapse. In one embodiment of a DANNA array of such circuit elements, (wherein a circuit element may be digital), a destination neuron may be connected to a first neuron by a first synapse in one dimension a second destination neuron may be connected to the first neuron by a second synapse in a second dimension to form linked columns and rows of neuron/synapse circuit elements. In one embodiment, the rows and columns of circuit elements have read registers that are linked together by signal lines and clocked and controlled so as to output columnar data to an output register when a neuron/synapse data value is stored in the read register.

Abstract: A circuit element of a multi-dimensional dynamic adaptive neural network array (DANNA) may comprise a neuron/synapse select input functional to select the circuit element to function as one of a neuron and a synapse. In one embodiment of a DANNA array of such circuit elements, (wherein a circuit element or component thereof may be analog or digital), a destination neuron may be connected to a first neuron by a first synapse in one dimension, a second destination neuron may be connected to the first neuron by a second synapse in a second dimension and, optionally, a third destination neuron may be connected to the first neuron by a third synapse. The DANNA may thus form multiple levels of neuron and synapse circuit elements. In one embodiment, multiples of eight inputs may be selectively received by the circuit element selectively functioning as one of a neuron and a synapse.

Abstract: A digital circuit element of a two dimensional dynamic adaptive neural network array (DANNA) may comprise a neuron/synapse select input functional to select the digital circuit element to function as one of a neuron and a synapse. In one embodiment of a DANNA array of such digital circuit elements, a destination neuron may be connected to a first neuron by a first synapse in one dimension, a second destination neuron may be connected to the first neuron by a second synapse in a second dimension and, optionally, a third destination neuron may be connected to the first neuron by a third synapse thus forming multiple levels of neuron and synapse digital circuit elements. In one embodiment, multiples of eight inputs may be selectively received by the digital circuit element selectively functioning as one of a neuron and a synapse.

Abstract: A method and apparatus for constructing a neuroscience-inspired artificial neural network (NIDA) or a dynamic adaptive neural network array (DANNA) or combinations of substructures thereof comprises one of constructing a substructure of an artificial neural network for performing a subtask of the task of the artificial neural network or extracting a useful substructure based on one of activity, causality path, behavior and inputs and outputs. The method includes identifying useful substructures in artificial neural networks that may be either successful at performing a subtask or unsuccessful at performing a subtask. Successful substructures may be implanted in an artificial neural network and unsuccessful substructures may be extracted from the artificial neural network for performing the task.

Abstract: A method and apparatus for constructing one of a neuroscience-inspired artificial neural network and a neural network array comprises one of a neuroscience-inspired dynamic architecture, a dynamic artificial neural network array and a neural network array of electrodes associated with neural tissue such as a brain, the method and apparatus having a special purpose display processor. The special purpose display processor outputs a display over a period of selected reference time units to demonstrate a neural pathway from, for example, one or a plurality of input neurons through intermediate destination neurons to an output neuron in three dimensional space. The displayed neural network may comprise neurons and synapses in different colors and may be utilized, for example, to show the behavior of a neural network for classifying hand-written digits between values of 0 and 9 or recognizing vertical/horizontal lines in a grid image of lines.

Abstract: A method and apparatus for constructing a neuroscience-inspired artificial neural network (NIDA) or a dynamic adaptive neural network array (DANNA) or combinations of substructures thereof comprises one of constructing a substructure of an artificial neural network for performing a subtask of the task of the artificial neural network or extracting a useful substructure based on one of activity, causality path, behavior and inputs and outputs. The method includes identifying useful substructures in artificial neural networks that may be either successful at performing a subtask or unsuccessful at performing a subtask. Successful substructures may be implanted in an artificial neural network and unsuccessful substructures may be extracted from the artificial neural network for performing the task.

Abstract: A circuit element of a multi-dimensional dynamic adaptive neural network array (DANNA) may comprise a neuron/synapse select input functional to select the circuit element to function as one of a neuron and a synapse. In one embodiment of a DANNA array of such circuit elements, (wherein a circuit element may be digital), a destination neuron may be connected to a first neuron by a first synapse in one dimension a second destination neuron may be connected to the first neuron by a second synapse in a second dimension to form linked columns and rows of neuron/synapse circuit elements. In one embodiment, the rows and columns of circuit elements have read registers that are linked together by signal lines and clocked and controlled so as to output columnar data to an output register when a neuron/synapse data value is stored in the read register.

Abstract: A circuit element of a multi-dimensional dynamic adaptive neural network array (DANNA) may comprise a neuron/synapse select input functional to select the circuit element to function as one of a neuron and a synapse. In one embodiment of a DANNA array of such circuit elements, (wherein a circuit element or component thereof may be analog or digital), a destination neuron may be connected to a first neuron by a first synapse in one dimension, a second destination neuron may be connected to the first neuron by a second synapse in a second dimension and, optionally, a third destination neuron may be connected to the first neuron by a third synapse. The DANNA may thus form multiple levels of neuron and synapse circuit elements. In one embodiment, multiples of eight inputs may be selectively received by the circuit element selectively functioning as one of a neuron and a synapse.

Abstract: A digital circuit element of a two dimensional dynamic adaptive neural network array (DANNA) may comprise a neuron/synapse select input functional to select the digital circuit element to function as one of a neuron and a synapse. In one embodiment of a DANNA array of such digital circuit elements, a destination neuron may be connected to a first neuron by a first synapse in one dimension, a second destination neuron may be connected to the first neuron by a second synapse in a second dimension and, optionally, a third destination neuron may be connected to the first neuron by a third synapse thus forming multiple levels of neuron and synapse digital circuit elements. In one embodiment, multiples of eight inputs may be selectively received by the digital circuit element selectively functioning as one of a neuron and a synapse.

Abstract: A method and apparatus for constructing one of a neuroscience-inspired artificial neural network and a neural network array comprises one of a neuroscience-inspired dynamic architecture, a dynamic artificial neural network array and a neural network array of electrodes associated with neural tissue such as a brain, the method and apparatus having a special purpose display processor. The special purpose display processor outputs a display over a period of selected reference time units to demonstrate a neural pathway from, for example, one or a plurality of input neurons through intermediate destination neurons to an output neuron in three dimensional space. The displayed neural network may comprise neurons and synapses in different colors and may be utilized, for example, to show the behavior of a neural network for classifying hand-written digits between values of 0 and 9 or recognizing vertical/horizontal lines in a grid image of lines.

Abstract: A data storage device for recording to and reading from magnetic thread includes a head assembly having an opening through which the magnetic thread passes. Transducing elements are positioned around the inner surface of the opening and interact with longitudinally-extending parallel tracks formatted around the surface of the magnetic thread. If the number of tracks is greater than the number of transducing elements, the transducing elements may be rotatable about the magnetic thread to position the transducing elements to interact with other tracks. The head assembly may open to aid positioning the magnetic thread within the opening in the head assembly during loading. If desired, multiple head assemblies may be placed in the thread path to improve data throughput. The magnetic thread may be formed with a non-circular cross-section and the opening in the head assembly may have a corresponding cross-section to reduce twisting of the magnetic thread as it passes through the opening.

Abstract: A method and system in a distributed shared-memory data processing system are disclosed having a single operating system being executed simultaneously by a plurality of processors included within a plurality of coupled processing nodes for determining a utilization of each memory location included within a shared-memory included within each of the plurality of nodes by each of the plurality of nodes. The operating system processes a designated application utilizing the plurality of nodes. During the processing, for each of the plurality of nodes, a determination is made of a quantity of times each memory location included within a shared-memory included within each of the plurality of nodes is accessed by each of the plurality of nodes.

Abstract: A method and system in a distributed shared-memory data processing system are disclosed for determining a utilization of each of a plurality of coupled processing nodes by one of a plurality of executed threads. The system includes a single operating system being executing simultaneously by a plurality of processors included within each of the processing nodes. The operating system processes one of the plurality of threads utilizing one of the plurality of nodes. During the processing, for each of the nodes, a quantity of times the one of the plurality of threads accesses a shared-memory included with each of the plurality of nodes is determined.

Abstract: A method and system are disclosed for reading data from an m-byte memory device utilizing a processor having an n-byte data bus, where m is less than or equal to n, which do not require the processor to support special bus cycles, bus select signals, or dynamic bus sizing. Responsive to an initiating signal from the processor to an interface controller, a plurality of data latches are initialized by a control signal. An address counter is also initialized. The memory device is activated by a control signal. Latching of data by one of the plurality of data latches is enabled. Data associated with an address indicated by the address counter is then latched from the memory device utilizing the enabled data latch. The address counter is incremented. The enabling, latching, and incrementing steps are repeated until n bytes of data are latched. When n bytes of data are latched, the processor is signaled that n bytes of data are valid to read.

Abstract: A method and system are provided for self-timed processing. An operation is executed with a functional unit. A timing of the operation execution is simulated with a tracking element, and a tracking signal is output. A sequencing signal is varied to the functional unit in response to the tracking signal.

Abstract: A system and method for protecting individual segments of a contiguous I/O address space on a system bus using the page access protection resources of a processor operating on a processor bus address space. The contiguous I/O address space is segmented and mapped by translation into the processor address space by distributing I/O segments non-contiguously among successive processor bus pages. Individual I/O address space segments, as may be associated with I/O ports, are protected directly by the processor through the selective enablement of page protection for correspondingly mapped ports.

Abstract: A method and system are provided for prefetching information in a processing system. A first memory has multiple first locations. At least one of the first locations stores information including an address of a different first location, the different first location having been referenced in the first memory after a previous reference to the one first location. A second memory has at least one second location storing information from the one first location, including the address. Information is prefetched to the second memory from the address of the first memory, in response to a reference to the second location.

Abstract: The capacity of cache memory supported by a cache controller can be increased by offsetting the relationship between CPU address output terminals and address input terminals of the cache controller and correspondingly doubling the cache line size. In some cases, additional logic generates a hidden memory cycle so as to fetch from memory that number of bytes equal to the new line size regardless of the width of the data bus. The hidden memory cycle is initiated by a read miss and further logic generates a memory address which is not generated by the CPU. The hidden memory cycle is maintained transparent to the CPU and cache controller by inhibiting the change in a READY signal until completion of both the normal memory cycle and the hidden memory cycle.

Abstract: A system and method for connecting a short word length memory to a significantly wider bus operated in an address/data multiplexing mode. A mode of operation is defined for the bus whereby the bus lines are divided for purposes of memory accessing into a data group and an address group. The data group is operable bidirectionally to read or write memory, using the addresses provided on the group of address lines. This architecture and practice is particularly suited for a boot ROM used with processors, in that such ROMs are normally of relatively short word length while the processors are of relatively long word length and are accordingly connected to buses of similar long word length. Bridge logic interfaces the processor bus to the ROM for sequencing, timing and supplemental control in converting the data from the ROM format to the processor format.

Abstract: A microcomputer system employing an 80386 CPU and an 82385 cache controller has the capability of functioning with dynamic bus sizing (where the CPU interacts with devices which may or may not be 32-bits wide), as well as posted write capability. Unfortunately, the two capabilities have the possibility of an incompatibility if a write cycle is posted to a device which cannot transfer 32 bits on a single cycle. The present invention provides logic to overcome this incompatibility. An address decoder is provided to decode the tag portion of an address asserted on a CPU local bus to determine if the asserted address is inside or outside a range of addresses which define cacheable devices. Any cacheable device is by definition 32 bits wide and therefore posted writes are allowed only to cacheable devices. Accordingly, the microcomputer system employing the invention posts write cycles to cacheable devices; write cycles to non-cacheable devices are inhibited from being posted.