Abstract: A health information gathering system for gathering information from at least one user. The health information gathering system includes a database storing information relating to a user and pertaining to at least two of the areas of information selected from a group consisting of nutritional information, psychological information, occupational information, physical information and personal history information, access to the information stored in the database being controlled by the user. The user can input information pertaining to the at least two areas of information selected from the group consisting of nutritional information, psychological information, occupational information, physical information and personal history information into the database, and the user can retrieve information from the database.

Abstract: A health information gathering system for gathering information from at least one user. The health information gathering system includes a database storing information relating to a user and pertaining to at least two of the areas of information selected from a group consisting of nutritional information, psychological information, occupational information, physical information and personal history information, access to the information stored in the database being controlled by the user. The user can input information pertaining to the at least two areas of information selected from the group consisting of nutritional information, psychological information, occupational information, physical information and personal history information into the database, and the user can retrieve information from the database.

Abstract: A health information gathering system for gathering information from at least one user. The health information gathering system includes a database storing information relating to a user and pertaining to at least two of the areas of information selected from a group consisting of nutritional information, psychological information, occupational information, physical information and personal history information, access to the information stored in the database being controlled by the user. The user can input information pertaining to the at least two areas of information selected from the group consisting of nutritional information, psychological information, occupational information, physical information and personal history information into the database, and the user can retrieve information from the database.

Abstract: A current mirror compensation circuit is disclosed herein which automatically adjusts the operating conditions of a current mirror so as to compensate for the voltage dependent current characteristics of a current load which a current mirror output is intended to match. In one embodiment, this compensation circuit compares a voltage level at the output of a current source with a voltage level at a corresponding node in the current programming portion of a current mirror. If a difference in these voltages is detected, the compensation circuit adjusts the current flow through the current programming portion of the current mirror to be equal to the output current through the current source. Therefore, since the current mirror output portion mirrors the current through the programming position, the currents through the output portion will match the current through the current source.

Abstract: A state machine is configured with a phase-locked loop clock signal generator which can operate at a rate faster than an externally generated reference clock signal applied to the phase-locked loop. The output of the phase-locked loop is used to trigger registers coupled to the state machine at a selected rate to enable signals at output terminals of the state machine to be updated at a rate different than the rate of the externally generated reference clock signal.

Abstract: A phase-locked loop responsive to both phase and frequency difference between the incoming signal and the feedback signal is provided. Using a reference signal, this phase-locked loop accepts a wide range of frequencies similar to a phase-locked loop having a phase frequency detector, and also achieves the noise performance of a phase-locked loop having only a simple phase detector. In one embodiment, the phase-locked loop is a combination including first and second phase-locked loops. The reference signal is provided to the first phase-locked loop, which includes a phase frequency detector. This first phase-locked loop is used to control a second phase-locked loop, which includes a phase detector. A voltage clamp can also be provided to enhance the ability to lock a signal among several signals, or from a noisy background.

Abstract: In a current pump, three separate current sources, each providing an identical current, are used. A first current pump is provided between an output load and a positive power supply terminal to provide a positive current to a load. To enable the current pump to provide a zero current to the load or withdraw a current from the load, second and third current pumps are provided in parallel between the load and a ground terminal. Associated switches couple these second and third current sources to the load. Thus, three states of the current pump are available which provide either a positive current, a negative current, or a zero current to a load.

Abstract: The present electrical circuit functions to couple together circuits which may have different signal operating levels, such as circuits having small-swing ECL operating levels and large-swing TTL operating levels. The present circuit outputs a signal which is virtually unaffected by any non-ideal characteristics of transistors comprising the circuit.

Abstract: A switch means is disclosed which enables two or more terminals normally having a wide operating voltage to be connected by a pass transistor. A biasing means applies a voltage to the gate of the pass transistor which turns on the pass transistor without forward biasing any inherent diodes within the pass transistor.

Abstract: The present invention includes circuitry implemented in gallium arsenide technology for generating various substantially constant reference voltage and a substantially constant reference current for applications thereof as needed.

Abstract: In one embodiment, a semiconductor device which generates a substantially constant reference voltage over a broad temperature range upon application of a power supply voltage thereto, wherein a current substantially inversely proportional to the value of a load resistor is drawn through the resistor to generate a substantially constant voltage across the resistor. The current through the resistor is the sum of a first current and a second current. The first current is determined by the absolute value of the threshold voltage of a depletion mode FET (DFET) in conjunction with an associated first resistor. The second current is determined by the threshold voltage of an enhancement mode FET (EFET) in conjunction with an associated second resistor. As the temperature of the device changes the first and second currents will change in opposite directions with the sum being changed inversely proportional to the change in resistance with temperature of the load resistor.

Abstract: A reset circuit incorporated into a latch circuit which comprising a follow portion and a hold portion and generates an output signal at an output terminal in response to an input data signal and a clock signal. A reset signal is applied, via a diode, to the output terminal which causes the output terminal to immediately assume the state of the reset signal without any intervening gate delay.

Abstract: This invention discloses a push pull logic circuit which includes a capacitor connected to the output signal lead of the circuit, and also a plurality of diodes, in parallel with the capacitor and connected to the output signal lead.

Abstract: This invention discloses a logic circuit including first, second and third transistors with the control terminals of two of those transistors being connected to the input signal lead, with the output signal lead being connected to one of the current handling terminals of one of those transistors, and with a load device connected to the respective current handling terminals of those two transistors and one of the voltage supply terminals.

Abstract: A programmable array including FET devices arranged in rows and columns is disclosed in which first and second bit lines for cells in adjacent first and second columns are arranged so that a fusible link connecting a cell of a column to its associated bit line crosses the bit line associated with the adjacent column of cells. By doing so, two fuses may now be located in an area which was heretofore occupied by a single fuse.

Abstract: A multiplexing type circuit includes circuit portions having input and output leads associated therewith, to allow testing of the individual circuit portions, and further includes laser programmable fuses which allow selective disconnection of certain input and output leads as chosen to disconnect circuit portions from the overall circuit as appropriate.

Abstract: An improved logic circuit is disclosed, of the type in which one or more input signals, generated by one or more input signal generator circuits, are referenced to a threshold voltage, determined by a threshold voltage generator circuit, to determine whether said one or more input signals are in a high or low state. In this improved logic circuit, the time constants of the input signal generator circuits are matched with those of the threshold voltage generator circuit so that any power supply perturbations commonly applied to the input signal generator circuits and threshold voltage generator circuit, such as due to the switching on or off of output loads, will result in these circuits having substantially identical frequency responses and amplitude versus time responses.

Abstract: The present electrical circuit is capable of coupling operation between other circuits which may have different signal levels, such as small-swing ECL-like signals and large-swing TTL-like signals.

Abstract: The present invention includes circuitry wherein a pair of voltage supply terminals are included, with a first current source connected to one voltage supply terminal and a second current source connected to the other voltage supply terminal. A load connects the first and second currect sources. A field effect transistor has a first current handling terminal connected between the first current source and load, a second current handling terminal connected to the other voltage supply terminal, and a current control terminal connected between the load and the second current source. The second current source is of the type wherein the current thereacross is substantially independent of changes in voltage thereacross.

Abstract: A state machine is configured with a phase-locked loop clock signal generator which can operate at a rate faster than an externally generated reference clock signal applied to the phase-locked loop. The output of the phase-locked loop is used to trigger registers coupled to the state machine at a selected rate to enable signals at output terminals of the state machine to be updated at a rate different than the rate of the externally generated reference clock signal.