Abstract: A method of forming a charge balance region in an active semiconductor device includes: forming an epitaxial region including material of a first conductivity type on an upper surface of a substrate of the semiconductor device; forming multiple recessed features at least partially through the epitaxial region; depositing a film comprising material of a second conductivity type on a bottom and/or sidewalls of the recessed features using atomic layer deposition; and performing thermal processing such that at least a portion of the film deposited on the bottom and/or sidewalls of each of the recessed features forms a region of the second conductivity type in the epitaxial layer which follows a contour of the recessed features, the region of the second conductivity type, in conjunction with the epitaxial layer proximate the region of the second conductivity type, forming the charge balance region.

Abstract: A method of forming a charge balance region in an active semiconductor device includes: forming an epitaxial region including material of a first conductivity type on an upper surface of a substrate of the semiconductor device; forming multiple recessed features at least partially through the epitaxial region; depositing a film comprising material of a second conductivity type on a bottom and/or sidewalls of the recessed features using atomic layer deposition; and performing thermal processing such that at least a portion of the film deposited on the bottom and/or sidewalls of each of the recessed features forms a region of the second conductivity type in the epitaxial layer which follows a contour of the recessed features, the region of the second conductivity type, in conjunction with the epitaxial layer proximate the region of the second conductivity type, forming the charge balance region.

Abstract: A packaged power supply module (100) comprising a chip (110) with a first power field effect transistor (FET) and a second chip (120) with a second FET conductively attached side-by-side onto a conductive carrier (130), the transistors having bond pads of a first area (210) and the carrier having bond pads of a second area (230) smaller than the first area. Conductive bumps (114, 115, 124, 125) attached to the transistor bond pads and conductive bumps (126) attached to the carrier bond pads have equal volume and are coplanar (150), the bumps on the transistor pads having a first height and the bumps on the carrier pads having a second height greater than the first height.

Abstract: A packaged power supply module (100) comprising a chip (110) with a first power field effect transistor (FET) and a second chip (120) with a second FET conductively attached side-by-side onto a conductive carrier (130), the transistors having bond pads of a first area (210) and the carrier having bond pads of a second area (230) smaller than the first area. Conductive bumps (114, 115, 124, 125) attached to the transistor bond pads and conductive bumps (126) attached to the carrier bond pads have equal volume and are coplanar (150), the bumps on the transistor pads having a first height and the bumps on the carrier pads having a second height greater than the first height.

Abstract: A non-linear transmission line terminator (10) is provided in which voltages appearing on a transmission line are sensed. If the voltage level sensed is equal to a predetermined voltage, the non-linear transmission line terminator (10) couples a reference voltage to the transmission line. If the sensed voltage is less than the predetermined voltage, the non-linear transmission line terminator (10) delivers current to the transmission line having a magnitude related non-linearly to the sensed voltage.

Abstract: A method and apparatus for a circuit physically realizing a virtual ground function producing a virtual ground voltage halfway between the supply and common voltages and having improved accuracy and stability is described. A stable bias current source is coupled to a precision resistor voltage divider network, which is used as a voltage reference generator to produce a virtual ground voltage of a precise value. This reference voltage is coupled to an operational amplifier configured in a unity gain configuration. The circuit thus created offers numerous advantages over the virtual ground circuits in use in the prior art. An integrated circuit implementing this circuit is described, and alternative packaging embodiments are disclosed. Other embodiments are also disclosed.

Abstract: A method and apparatus for a circuit physically realizing a virtual ground function and having improved accuracy and stability is described. A stable bias current source is coupled to a bandgap reference generator and resistances to produce a virtual ground voltage of a precise value, this voltage is then coupled to an operational amplifier configured in a unity gain configuration. The circuit thus created offers numerous advantages over the virtual ground circuits in use in the prior art. An integrated circuit implementing this circuit is described, and alternative packaging embodiments are disclosed. Other embodiments are also disclosed.