Patents by Inventor Mark E. Hastings

Mark E. Hastings has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10345377
    Abstract: A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manger coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: July 9, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Harold M. Kutz, Timothy John Williams, Bert S. Sullam, Warren S. Snyder, James H. Shutt, Bruce E. Byrkett, Monte Mar, Eashwar Thiagarajan, Nathan Wayne Kohagen, David G. Wright, Mark E. Hastings, Dennis R. Seguine
  • Publication number: 20170286344
    Abstract: An integrated circuit device may include a reconfigurable analog signal switching fabric comprising a plurality of global buses that are selectively connected to external pins by pin connection circuits in response to changeable analog routing data, and a plurality of local buses that are selectively connected to analog blocks and/or global buses by routing connection circuits in response to the analog routing data; and at least one processor circuit that executes predetermined operations in response to instruction data.
    Type: Application
    Filed: March 20, 2017
    Publication date: October 5, 2017
    Applicant: Cypress Semiconductor Corporation
    Inventors: Bert S. Sullam, Harold M. Kutz, Timothy John Williams, James H. Shutt, Bruce E. Byrkett, Melany Ann Richmond, Nathan Wayne Kohagen, Mark E. Hastings, Eashwar Thiagarajan, Warren S. Snyder
  • Patent number: 9634667
    Abstract: An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, and at least one reconfigurable analog circuit block selected from: a continuous time (CT) block comprising a plurality of reconfigurable amplifier circuits and a discrete time block comprising amplifiers with a reconfigurable switch network; an analog multiplexer (MUX) configured to selectively connect any of a plurality of input/outputs (I/Os) of the IC device to the analog blocks, the analog MUX including at least one low noise signal path pair having a lower resistance than other signal paths of the analog MUX; at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; a digital section comprising digital circuits; and a processor interface coupled to the analog blocks.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: April 25, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Eashwar Thiagarajan, Harold M. Kutz, Hans Klein, Jaskarn Singh Johal, Jean-Paul Vanitegem, Kendall V. Castor-Perry, Mark E. Hastings, Amsby D. Richardson, Jr., Anasuya Pai Maroor, Ata Khan, Dennis R. Seguine, Bruce E. Byrkett, Carl Ferdinand Liepold, Hans Van Antwerpen
  • Publication number: 20160329900
    Abstract: An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, a plurality of reconfigurable analog circuit blocks, at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; and a digital section comprising digital circuits; wherein each analog block includes dedicated of signal lines coupled to the at least one analog routing block.
    Type: Application
    Filed: March 26, 2015
    Publication date: November 10, 2016
    Inventors: Eashwar Thiagarajan, Harold M. Kutz, Hans Klein, Jaskarn Singh Johal, Jean-Paul Vanitegem, Kendall V. Castor-Perry, Mark E. Hastings, Amsby D. Richardson, JR., Anasuya Pai Maroor, Ata Khan, Dennis R. Seguine, Onur Ozbek, Carl Ferdinand Liepold
  • Patent number: 9473144
    Abstract: An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, a plurality of reconfigurable analog circuit blocks, at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; and a digital section comprising digital circuits; wherein each analog block includes dedicated of signal lines coupled to the at least one analog routing block.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: October 18, 2016
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Eashwar Thiagarajan, Harold M. Kutz, Hans Klein, Jaskarn Singh Johal, Jean-Paul Vanitegem, Kendall V. Castor-Perry, Mark E. Hastings, Amsby D. Richardson, Jr., Anasuya Pai Maroor, Ata Khan, Dennis R. Seguine, Onur Ozbek, Carl Ferdinand Liepold
  • Publication number: 20160065216
    Abstract: An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, and at least one reconfigurable analog circuit block selected from: a continuous time (CT) block comprising a plurality of reconfigurable amplifier circuits and a discrete time block comprising amplifiers with a reconfigurable switch network; an analog multiplexer (MUX) configured to selectively connect any of a plurality of input/outputs (I/Os) of the IC device to the analog blocks, the analog MUX including at least one low noise signal path pair having a lower resistance than other signal paths of the analog MUX; at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; a digital section comprising digital circuits; and a processor interface coupled to the analog blocks.
    Type: Application
    Filed: March 26, 2015
    Publication date: March 3, 2016
    Inventors: Eashwar Thiagarajan, Harold M. Kutz, Hans Klein, Jaskarn Singh Johal, Jean-Paul Vanitegem, Kendall V. Castor-Perry, Mark E. Hastings, Amsby D. Richardson, JR., Anasuya Pai Maroor, Ata Khan, Dennis R. Seguine, Bruce E. Byrkett, Carl Ferdinand Liepold, Hans Van Antwerpen
  • Patent number: 9143134
    Abstract: A system and apparatus are described for providing greater flexibility and performance in a mixed-signal array through improved and highly configurable routing, control elements and signal processing capabilities.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: September 22, 2015
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Harold M. Kutz, Timothy J. Williams, Bert S. Sullam, Warren S. Snyder, James H. Shutt, Bruce E. Byrkett, Monte Mar, Eashwar Thiagarajan, Nathan Kohagen, David G. Wright, Mark E. Hastings, Dennis Raymond Seguine
  • Patent number: 8890600
    Abstract: A programmable device, having an analog component coupled with an analog bus and a digital component coupled with a digital bus together with a set of IO pads, each of which capable of being coupled to a bus line of one segment of the analog bus as well as to at least one digital bus line, and where the analog bus is capable of being used to connect a pair of the IO pads to each other.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: November 18, 2014
    Assignee: Cypress Semicondductor Corporation
    Inventors: Timothy J. Williams, Harold Kutz, David G. Wright, Eashwar Thiagarajan, Warren S. Snyder, Mark E. Hastings
  • Patent number: 8441298
    Abstract: In one example, a chip includes an integrated analog component configured to communicate over an internal analog bus of the chip. A plurality of I/O pads located on the chip is configured to provide a connected device access to the integrated analog component. A plurality of transmission gates configured to selectively connect the I/O pads to a bus line of the analog bus.
    Type: Grant
    Filed: July 1, 2009
    Date of Patent: May 14, 2013
    Assignee: Cypress Semiconductor Corporation
    Inventors: Timothy Williams, David G. Wright, Harold Kutz, Eashwar Thiagarajan, Warren Snyder, Mark E. Hastings
  • Patent number: 7259547
    Abstract: A system and method for dynamically lock the sample rate of an analog to digital (ADC) converter to an input frequency. Specifically, a system for measuring power is disclosed. The system includes an ADC converter, a measuring module, an ADC cycle counter, and a calculation block coupled together. The ADC converter samples an analog input line signal. The measuring module measures a predetermined number of line cycles of the analog input line signal. The ADC cycle counter measures an actual sample count of the analog input line signal by the ADC converter over the predetermined number of line cycles. The calculation block determines an error rate between the actual sample count and an ideal sample count that is based on a predetermined over sample rate.
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: August 21, 2007
    Assignee: Cypress Semiconductor Corporation
    Inventors: Kevin Summers, Mark E. Hastings
  • Patent number: 7068205
    Abstract: A circuit, method and microcontroller apparatus for performing an analog to digital conversion with continuously variable resolution is disclosed. The circuit includes a integrating modulator for converting an analog input signal, corresponding to an input voltage, to a digital signal at its output over an integrate time. The circuit also includes a counter with an enable input coupled to the integrating modulator output. The counter accumulates the number of cycles where the digital signal is positive during the sample period and provides a corresponding conversion result. Further, the circuit has a pulse width modulator; its output gates a clock to the counter enable input. The pulse width modulator is user programmable on-the-fly to set said integrate time and said sample period.
    Type: Grant
    Filed: June 22, 2004
    Date of Patent: June 27, 2006
    Assignee: Cypress Semiconductor Corp.
    Inventors: Mark E. Hastings, David Van Ess
  • Patent number: 6772251
    Abstract: A shared wire serial interface between two devices that share a system clock and a single bi-directional serial data line. The clock drives both the system and the interface and is provided over a single clock wire. One device operates as a master, the other as a slave. Since master and slave share the same clock, clock drift error will be zero. Although the start of a data transfer is asynchronous with regard to the system clock, the data transfer itself, is synchronous. In one embodiment, the bit transfer rate is ⅛th the system clock speed in one example and is generated by a state machine, however, any divide may be used. The state machine also signals the output enablers which interleave the data bits on the serial data line. The flow of data on a single data line of the interface is bi-directional in that data from the master is bit interleaved with data from the slave.
    Type: Grant
    Filed: May 4, 2001
    Date of Patent: August 3, 2004
    Assignee: Cypress Semiconductor Corporation
    Inventors: Mark E. Hastings, Timothy E. Nelson
  • Patent number: 6738834
    Abstract: A dynamically and independently reconfigurable multi-mode device, and a method thereof. The device can include a controller for selecting a mode of operation. The device is configured according to the mode of operation. The configuration information corresponding to the mode of operation resides on the device such that the configuring is accomplished independent of a host device. The device also can include interface circuitry for simulating disconnection of the device from, and reconnection of the device to, the host device. The selected mode of operation is implemented between the simulated disconnection and reconnection.
    Type: Grant
    Filed: July 15, 2002
    Date of Patent: May 18, 2004
    Assignee: Cypress Microsystems
    Inventors: Timothy J. Williams, Mark E. Hastings
  • Patent number: 5931623
    Abstract: An apparatus for spiral binding a stack of papers together as a unit. The apparatus includes a coil feeder for feeding a spiral coil into the holes in the stack of papers, a pin extension and retraction mechanism, a coil cutter mechanism, and a paper thickness measuring and sizing mechanism. The spiral binding unit includes an aperture through which a spiral coil is inserted between a feed shaft and a rotatably mounted roller. The roller may be rotated in a pulsed manner. As the coil is inserted, the roller pushes the spiral coil into contact with the feed shaft. As the roller rotates, the coil is guided around a plurality of spiral guides that cause the coil to spiral into the holes in the stack of paper. The guides and any other surfaces which the end of the coil contacts along its path may have chamfered edges. The pin extension and retraction mechanism includes a plurality of curved locator pins that are movable between an extended and a retracted position.
    Type: Grant
    Filed: October 10, 1996
    Date of Patent: August 3, 1999
    Assignee: Unicoil, Inc.
    Inventors: Mark E. Hastings, Randy C. Peterson, Kevin L. Engelbert, John H. Mar
  • Patent number: 5705903
    Abstract: An electric brake circuit (10) for bringing an alternating current (AC) motor (12) to a rapid halt. When the AC motor is turned on, a braking capacitor (C1) is charged to a preselected voltage. A shunt regulator (18) prevents the braking capacitor from overcharging by shunting charging current to ground once the braking capacitor reaches the preselected voltage. In a preferred embodiment, a limit circuit (20) turns off the charging current on the subsequent positive phase of the AC line voltage powering the electric brake. By shutting off current flow to the circuit when the preselected voltage on the capacitor is reached, power consumption and size of the circuit are minimized.
    Type: Grant
    Filed: February 12, 1996
    Date of Patent: January 6, 1998
    Assignee: Unicoil, Inc.
    Inventor: Mark E. Hastings
  • Patent number: 5695308
    Abstract: An apparatus for spiral binding a stack of papers together as a unit. The apparatus includes a spiral binding unit for feeding a spiral coil into the holes in the stack of papers, a pin extension and retraction mechanism, a coil cutter mechanism, and a paper thickness measuring and sizing mechanism. The spiral binding unit includes an aperture through which a spiral coil is inserted between a feed shaft and a rotatably mounted roller. As the coil is inserted, the roller pushes the spiral coil into contact with the feed shaft. As the roller rotates, the coil is guided around a plurality of spiral guides that cause the coil to spiral into the holes in the stack of paper. The pin extension and retraction mechanism includes a plurality of locator pins that are movable between an extended and a retracted position. In the extended position, the pins extend up through the holes in the stack of papers. The locator pins are mounted on pivotally mourned levers. The levers are in turn rotated by a cam shaft.
    Type: Grant
    Filed: October 6, 1995
    Date of Patent: December 9, 1997
    Assignee: Unicoil, Inc.
    Inventors: Mark E. Hastings, Randy C. Peterson, Kevin L. Engelbert, John H. Mar
  • Patent number: 5584632
    Abstract: An apparatus (10) for spiral binding a stack of papers (24) together as a unit. The apparatus includes a punch (12) for punching a plurality of holes (23) along one edge of the stack of papers and a spiral binding unit (14) for feeding a spiral coil (36) into the holes. The spiral binding unit (14) includes an aperture (44) through which a coil is inserted between a shoe (74) and a rotatably mounted roller (72). As the coil (36) is inserted, the shoe (74) pushes the coil into contact with the roller (72). As the roller (72) rotates, the coil (36) is guided through a series of slots (86) which cause the coil to spiral into the holes in the stack of paper. The punch (12) includes a ramp (186) that presses a series of punch pins (188) through the stack of papers. The ramp (186) includes a plurality of steps (222) that incline upwardly on either side of a center step (224). The punch first punches holes in the center of the stack of papers and then punches holes outward from either side of the center.
    Type: Grant
    Filed: October 11, 1994
    Date of Patent: December 17, 1996
    Assignee: Unicoil, Inc.
    Inventors: William P. Stiles, Sean M. MacLeod, Michael D. Nelson, Mark E. Hastings, David A. Herrin
  • Patent number: D365580
    Type: Grant
    Filed: October 11, 1994
    Date of Patent: December 26, 1995
    Assignee: Unicoil, Inc.
    Inventors: William P. Stiles, Sean M. MacLeod, Michael D. Nelson, Mark E. Hastings, David A. Herrin
  • Patent number: D376607
    Type: Grant
    Filed: October 6, 1995
    Date of Patent: December 17, 1996
    Assignee: Unicoil, Inc.
    Inventors: John H. Mar, Kevin L. Engelbert, Mark E. Hastings, Randy C. Peterson