Patents by Inventor Mark E. Hofmann

Mark E. Hofmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10796045
    Abstract: Systems and methods for efficient bi-directional property-based path tracing. The method includes reading a data structure corresponding to a circuit. The method also includes iteratively performing property accounting of properties as voltages propagate across devices in the circuit. The method also includes traversing series chains of similar devices in the circuit to reduce an iteration count and arrive at a circuit stability, wherein the circuit stability is determined when propagated user-specified and computed circuit properties (e.g. shortest distance) remain unchanged between subsequent iterations of the traversing. The method also includes traversing the data structure for propagated user-specified and computed property violations. The method also includes cataloging and reporting these violations in human-readable form.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: October 6, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Mark E. Hofmann, Sridhar Srinivasan
  • Patent number: 10534880
    Abstract: Aspects of the disclosed technology relate to techniques of voltage propagation-based reliability verification. Voltage values are propagated across components of a circuit design through global iterations until voltage values on nets of the circuit design are not changed from one global iteration to a next global iteration or one preset condition is met. At least one of the global iterations comprises local iterations for a subcircuit of the circuit design. The local iterations suspend when voltage values on nets of the subcircuit are not changed from one local iteration to a next local iteration or one preset condition is met. The propagated voltage values are then analyzed to detect problems in the circuit design.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: January 14, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Mark E. Hofmann, Sridhar Srinivasan, Gregory P. Hackney
  • Publication number: 20190377839
    Abstract: Systems and methods for efficient bi-directional property-based path tracing. The method includes reading a data structure corresponding to a circuit. The method also includes iteratively performing property accounting of properties as voltages propagate across devices in the circuit. The method also includes traversing series chains of similar devices in the circuit to reduce an iteration count and arrive at a circuit stability, wherein the circuit stability is determined when propagated user-specified and computed circuit properties (e.g. shortest distance) remain unchanged between subsequent iterations of the traversing. The method also includes traversing the data structure for propagated user-specified and computed property violations. The method also includes cataloging and reporting these violations in human-readable form.
    Type: Application
    Filed: June 5, 2019
    Publication date: December 12, 2019
    Inventors: Mark E. Hofmann, Sridhar Srinivasan
  • Patent number: 10360331
    Abstract: Aspects of the disclosed technology relate to techniques of scoped simulation-based ESD verification. ESD (electrostatic discharge) protection devices and I/O (input/output) circuitry are identified in a circuit design. Static simulation is performed on the I/O circuitry to determine voltage and current information for devices on current paths in the I/O circuitry based on point-to-point resistance values. Transient simulation is then performed on one or more of the ESD protection devices in the devices based on the voltage and current information and detailed parasitic information. The point-to-point resistance values and the detailed parasitic information are extracted based on a layout design for the circuit design and cross-reference information between circuit component identifiers and layout features. Results of the transient simulation are analyzed to identify ESD protection problems.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: July 23, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Sridhar Srinivasan, Mark E. Hofmann
  • Patent number: 10223485
    Abstract: Aspects of the disclosed technology relate to techniques of voltage-based reliability verification. Voltage values on nets of a circuit design are determined based on a combination of propagating voltage values across components of the circuit design and simulating one or more subcircuits. The one or more subcircuits are identified based on circuit topology recognition. The determined voltage values are analyzed to detect problems in the circuit design.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: March 5, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Sridhar Srinivasan, Mark E. Hofmann
  • Publication number: 20180218100
    Abstract: Aspects of the disclosed technology relate to techniques of voltage-based reliability verification. Voltage values on nets of a circuit design are determined based on a combination of propagating voltage values across components of the circuit design and simulating one or more subcircuits. The one or more subcircuits are identified based on circuit topology recognition. The determined voltage values are analyzed to detect problems in the circuit design.
    Type: Application
    Filed: January 31, 2017
    Publication date: August 2, 2018
    Inventors: Sridhar Srinivasan, Mark E. Hofmann
  • Publication number: 20180218101
    Abstract: Aspects of the disclosed technology relate to techniques of scoped simulation-based ESD verification. ESD (electrostatic discharge) protection devices and I/O (input/output) circuitry are identified in a circuit design. Static simulation is performed on the I/O circuitry to determine voltage and current information for devices on current paths in the I/O circuitry based on point-to-point resistance values. Transient simulation is then performed on one or more of the ESD protection devices in the devices based on the voltage and current information and detailed parasitic information. The point-to-point resistance values and the detailed parasitic information are extracted based on a layout design for the circuit design and cross-reference information between circuit component identifiers and layout features. Results of the transient simulation are analyzed to identify ESD protection problems.
    Type: Application
    Filed: January 31, 2017
    Publication date: August 2, 2018
    Inventors: Sridhar Srinivasan, Mark E. Hofmann
  • Publication number: 20180052950
    Abstract: Aspects of the disclosed technology relate to techniques of voltage propagation-based reliability verification. Voltage values are propagated across components of a circuit design through global iterations until voltage values on nets of the circuit design are not changed from one global iteration to a next global iteration or one preset condition is met. At least one of the global iterations comprises local iterations for a subcircuit of the circuit design. The local iterations suspend when voltage values on nets of the subcircuit are not changed from one local iteration to a next local iteration or one preset condition is met. The propagated voltage values are then analyzed to detect problems in the circuit design.
    Type: Application
    Filed: August 17, 2016
    Publication date: February 22, 2018
    Inventors: Mark E. Hofmann, Sridhar Srinivasan, Gregory P. Hackney
  • Publication number: 20180052951
    Abstract: Aspects of the disclosed technology relate to techniques of voltage propagation-based reliability verification. A circuit design is analyzed to identify circuit component chains. Voltage values are propagated across components of the circuit design based, at least in part, on treating the circuit component chains as virtual single components. The propagated voltage values are analyzed to detect problems in the circuit design.
    Type: Application
    Filed: August 17, 2016
    Publication date: February 22, 2018
    Inventors: Mark E. Hofmann, Sridhar Srinivasan, Gregory P. Hackney
  • Publication number: 20130318487
    Abstract: Techniques for analysis of an electrical circuit design are described, which techniques employ two phases: an initialization phase, and a check phase. During the initialization phase, a circuit design is examined to determine the predicted operating characteristics at various nodes within the design. If the design is hierarchically arranged, then the design is analyzed in a way that preserves its hierarchy. During the check phase, various implementations of the invention will check the determined operating characteristic values to see if they indicate that one or more design rules have been violated. A user may specify or “program” aspects of the analysis, both for the initialization phase and the check phase.
    Type: Application
    Filed: May 23, 2013
    Publication date: November 28, 2013
    Applicant: Mentor Graphics Corporation
    Inventors: Gregory P. Hackney, Mark E. Hofmann, Ziyang Lu, Dina Medhat