Patents by Inventor Mark E. Lewis

Mark E. Lewis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5328389
    Abstract: A compressible retention element of a diameter slightly greater than that of a cooperating cavity, having a low ratio of insertion to withdrawal forces. The retention element further provides insertion and withdrawal forces reduced from that found in the prior art. One embodiment of the retention element includes a cylindrical body, manufactured of a pliant material such as plastic or the like, having a wedge-shaped groove disposed axially along its length on one side and a planar region disposed axially along its length on an opposite side.
    Type: Grant
    Filed: July 1, 1993
    Date of Patent: July 12, 1994
    Assignee: Augat Inc.
    Inventors: Mark E. Lewis, David W. Mendenhall
  • Patent number: 5290193
    Abstract: A high density land grid array test socket comprises a leadless component contact socket assembly and a fixture. The contact socket assembly can be assembled with a variety of contact terminal end configurations and adapted for a desired mode of circuit board interface. In one embodiment, the test socket fixture includes a latching mechanism and a hinged lid assembly which allow quick and reliable manual installation of a device under test (DUT). An alternative embodiment includes snap latches, extension springs and alignment bushings which permit robotically controlled insertion and removal from the test socket. A bias clip or spring is incorporated in the test sockets for assuring proper alignment of the chip carrier with the contact socket assembly. The test socket creates reliable contacts with short electrical paths for low signal distortion and reduced chip loading.
    Type: Grant
    Filed: January 5, 1993
    Date of Patent: March 1, 1994
    Assignee: Augat Inc.
    Inventors: Jay Goff, Mark E. Lewis
  • Patent number: 5244403
    Abstract: The invention provides a socket for substrates such as single in-line memory modules, circuit boards, and similar components which are inserted into and rotated into fixed position on the socket. The socket housing includes end portions having improved structural integrity for externally mounting cooperative latch elements. The external mounting permits a greater variety of latch sizes and configurations to suit operational requirements. An exemplary latch is preferably metal and comprises a mounting collar having a compliant C-section which corresponds to a latch-receiving section or member on the socket housing, a detent for clasping a memory module, and a resilient section connected therebetween for biasing the detent so that it clasps the memory module in fixed position in the socket. The latch collar is mounted onto the cooperative section of the socket end portion, and the latch is thereby disposed exteriorly on the socket body.
    Type: Grant
    Filed: July 1, 1992
    Date of Patent: September 14, 1993
    Assignee: Augat Inc.
    Inventors: Gregory J. Smith, Wayne S. Alden, Mark E. Lewis, Michael J. Bellomo
  • Patent number: 5205742
    Abstract: A high density land grid array test socket comprises a leadless component contact socket assembly and a fixture. The contact socket assembly can be assembled with a variety of contact terminal end configurations and adapted for a desired mode of circuit board interface. In one embodiment, the test socket fixture includes a latching mechanism and a hinged lid assembly which allow quick and reliable manual installation of a device under test (DUT). An alternative embodiment includes snap latches, extension springs and alignment bushings which permit robotically controlled insertion and removal from the test socket. A bias clip or spring is incorporated in the test sockets for assuring proper alignment of the chip carrier with the contact socket assembly. The test socket creates reliable contacts with short electrical paths for low signal distortion and reduced chip loading.
    Type: Grant
    Filed: December 6, 1991
    Date of Patent: April 27, 1993
    Assignee: Augat Inc.
    Inventors: Jay Goff, Mark E. Lewis