Patents by Inventor Mark E. Masters

Mark E. Masters has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8536526
    Abstract: Methods for nanoprobing a device structure of an integrated circuit. The method may include scanning a primary charged particle beam across a first region of the device structure with at least one probe proximate to the first region and a second region of the device structure is masked from the primary charged particle beam. The method may further include collecting secondary electrons emitted from the first region of the device structure and the at least one probe to form a secondary electron image. The secondary electron image includes the first region and the at least one probe as imaged portions and the second region as a non-imaged portion. Alternatively, the second region may be scanned by the charged particle beam at a faster scan rate than the first region so that the second region is also an imaged portion of the secondary electron image.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: September 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Paul D. Bell, Mark E. Masters, David S. Patrick
  • Patent number: 8039334
    Abstract: A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: October 18, 2011
    Assignee: International Business Machines Corporation
    Inventors: Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Mark E. Masters
  • Publication number: 20110027951
    Abstract: A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.
    Type: Application
    Filed: October 12, 2010
    Publication date: February 3, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Mark E. Masters
  • Patent number: 7838943
    Abstract: A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.
    Type: Grant
    Filed: July 25, 2005
    Date of Patent: November 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Mark E. Masters
  • Publication number: 20100163727
    Abstract: Methods for nanoprobing a device structure of an integrated circuit. The method may include scanning a primary charged particle beam across a first region of the device structure with at least one probe proximate to the first region and a second region of the device structure is masked from the primary charged particle beam. The method may further include collecting secondary electrons emitted from the first region of the device structure and the at least one probe to form a secondary electron image. The secondary electron image includes the first region and the at least one probe as imaged portions and the second region as a non-imaged portion. Alternatively, the second region may be scanned by the charged particle beam at a faster scan rate than the first region so that the second region is also an imaged portion of the secondary electron image.
    Type: Application
    Filed: December 29, 2008
    Publication date: July 1, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul D. Bell, Mark E. Masters, David S. Patrick
  • Patent number: 7535016
    Abstract: A hybrid semiconductor structure which includes a horizontal semiconductor device and a vertical carbon nanotube transistor, where the vertical carbon nanotube transistor and the horizontal semiconductor device have at least one shared node is provided. The at least one shared node can include, for example, a drain, source or gate electrode of a FET, or an emitter, collector, or base of a bipolar transistor.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: May 19, 2009
    Assignee: International Business Machines Corporation
    Inventors: Toshiharu Furukawa, Mark C. Hakey, David V. Horak, Charles W. Koburger, III, Mark E. Masters, Peter H. Mitchell
  • Patent number: 7484423
    Abstract: A method and structure for an integrated circuit comprising a first transistor and an embedded carbon nanotube field effect transistor (CNT FET) proximate to the first transistor, wherein the CNT FET is dimensioned smaller than the first transistor. The CNT FET is adapted to sense signals from the first transistor, wherein the signals comprise any of temperature, voltage, current, electric field, and magnetic field signals. Moreover, the CNT FET is adapted to measure stress and strain in the integrated circuit, wherein the stress and strain comprise any of mechanical and thermal stress and strain. Additionally, the CNT FET is adapted to detect defective circuits within the integrated circuit.
    Type: Grant
    Filed: April 4, 2007
    Date of Patent: February 3, 2009
    Assignee: International Business Machines Corporation
    Inventors: Mark C. Hakey, Mark E. Masters, Leah M. P. Pastel, David P. Vallett
  • Patent number: 7247877
    Abstract: A method and structure for an integrated circuit comprising a first transistor and an embedded carbon nanotube field effect transistor (CNT FET) proximate to the first transistor, wherein the CNT FET is dimensioned smaller than the first transistor. The CNT FET is adapted to sense signals from the first transistor, wherein the signals comprise any of temperature, voltage, current, electric field, and magnetic field signals. Moreover, the CNT FET is adapted to measure stress and strain in the integrated circuit, wherein the stress and strain comprise any of mechanical and thermal stress and strain. Additionally, the CNT FET is adapted to detect defective circuits within the integrated circuit.
    Type: Grant
    Filed: August 20, 2004
    Date of Patent: July 24, 2007
    Assignee: International Business Machines Corporation
    Inventors: Mark C. Hakey, Mark E. Masters, Leah M. P. Pastel, David P. Vallett
  • Patent number: 7089138
    Abstract: A diagnostic system and method for testing an integrated circuit during fabrication thereof. The diagnostic system has at least one integrated circuit chip that has an electrical signature associated with it; a sacrificial circuit that is adjacent to the integrated circuit chip and has a known electrical signature associated with it and intentionally mis-designed circuitry; and a comparator adapted to compare the electrical signature of the integrated circuit chip with the known electrical signature of the sacrificial circuit, wherein a match in the electrical signature of the integrated circuit chip with the known electrical signature of the sacrificial circuit indicates that the integrated circuit chip is mis-designed. The diagnostic system further includes a semiconductor wafer that has a plurality of integrated circuit chips and a kerf area separating one integrated circuit chip from another integrated circuit chip. A mis-designed integrated circuit chip has abnormally functioning circuitry.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: August 8, 2006
    Assignee: International Business Machines Corporation
    Inventors: Pierre J. Bouchard, Mark C. Hakey, Mark E. Masters, Leah M. P. Pastel, James A. Slinkman, David P. Vallett
  • Patent number: 6627926
    Abstract: In a semiconductor device using fill shape patterns incorporated into wiring levels to increase the planarity of the wiring levels, the fill shapes are aligned from one wiring level to another wiring level to provide lines of sight to lower wiring levels for visual inspection. Also, in accordance with the invention, selected aligned fill shapes are interconnected with vias to form conductive stacks for contacting lower wiring level conductive wires from upper wiring levels in order to perform electrical test probing/diagnostics.
    Type: Grant
    Filed: February 16, 2001
    Date of Patent: September 30, 2003
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Hartswick, Mark E. Masters
  • Patent number: 6307162
    Abstract: An integrated distribution wiring system for a semiconductor substrate having a number of devices. The distribution system includes additional stripes which are arranged parallel to existing rails carrying power or signals to the devices. These stripes being separable from the rails may be used to make engineering changes such as repairs or modifications of the circuits in the devices or characterizing or diagnosing the devices.
    Type: Grant
    Filed: December 9, 1996
    Date of Patent: October 23, 2001
    Assignee: International Business Machines Corporation
    Inventors: Mark E. Masters, David P. Vallett
  • Publication number: 20010005052
    Abstract: In a semiconductor device using fill shape patterns incorporated into wiring levels to increase the planarity of the wiring levels, the fill shapes are aligned from one wiring level to another wiring level to provide lines of sight to lower wiring levels for visual inspection. Also, in accordance with the invention, selected aligned fill shapes are interconnected with vias to form conductive stacks for contacting lower wiring level conductive wires from upper wiring levels in order to perform electrical test probing/diagnostics.
    Type: Application
    Filed: February 16, 2001
    Publication date: June 28, 2001
    Inventors: Thomas J. Hartswick, Mark E. Masters
  • Patent number: 6251773
    Abstract: In a semiconductor device using fill shape patterns incorporated into wiring levels to increase the planarity of the wiring levels, the fill shapes are aligned from one wiring level to another wiring level to provide lines of sight to lower wiring levels for visual inspection. Also, in accordance with the invention, selected aligned fill shapes are interconnected with vias to form conductive stacks for contacting lower wiring level conductive wires from upper wiring levels in order to perform electrical test probing/diagnostics.
    Type: Grant
    Filed: December 28, 1999
    Date of Patent: June 26, 2001
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Hartswick, Mark E. Masters