Patents by Inventor Mark E. Prill

Mark E. Prill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5848072
    Abstract: A data-transmission system (100) including a master device (101) and at least one slave device (105) communicates messages having an address (1503, 1505) and data (1100) from the slave device (105) to the master device (101). The address (1503, 1505) is communicated synchronously and the data (1100) is communicated asynchronously. Furthermore, the address (1503, 1505) determines the control information and timing signal transmitted by the master device (101) to the slave devices (105-N).
    Type: Grant
    Filed: August 10, 1995
    Date of Patent: December 8, 1998
    Assignee: Motorola, Inc.
    Inventors: Mark E. Prill, Robert K. Krolopp
  • Patent number: 5546380
    Abstract: A unique method for supervising a cellular telephone call between a base station and a radio telephone of a TDMA cellular communications system includes the steps of determining (304) that the assigned time slot is expected to be received within a predetermined amount of time; detecting the presence of the assigned time slot (306) within the predetermined amount of time; detecting the presence of the assigned DVCC when the assigned time slot is detected (308); incrementing a bad slot counter (316) [if] responsive to the assigned time slot is not detected within the predetermined amount of time or [if] responsive to the assigned DVCC is not detected; and terminating the communication (322) [if] when the bad slot counter reaches a predetermined maximum value. A good slot counter is incremented (310) when the assigned DVCC is detected in a burst.
    Type: Grant
    Filed: January 24, 1995
    Date of Patent: August 13, 1996
    Assignee: Motorola, Inc.
    Inventors: Peter A. Tomasi, Mark E. Prill, Stephen V. Cahill
  • Patent number: 5150359
    Abstract: A multiplexed synchronous/asynchronous data bus is disclosed in which three bus lines are used to convey bidirectional synchronous data between at least two data devices at a relatively low data rate. Valid half duplex asynchronous data is applied at a higher data transfer rate to one of the three bus lines when only one of the bus lines is held in a logic high state.
    Type: Grant
    Filed: August 6, 1990
    Date of Patent: September 22, 1992
    Assignee: Motorola, Inc.
    Inventors: Gregory P. Wilson, Bryan A. Potratz, Thomas J. Walczak, Jeffery L. Mullins, Mark E. Prill