Abstract: A photodetector includes a first conductivity type semiconductor material (e.g., a p-type material) and one or more regions of semiconductor material of a second conductivity type (e.g., regions of n-type material), each forming a pn junction with the first conductivity type semiconductor material. The one or more regions collectively have a first layout area. One or more further regions of semiconductor material of the second conductivity type (e.g., further regions of n-type material) each form a pn junction with the first conductivity type semiconductor material. The one or more further regions collectively having a second layout area. A light blocking material covers the one or more further regions. The first layout area is greater than the second layout area.

Abstract: In the fabrication of a 0.10 micron CMOS integrated circuit, a high-energy plasma etch is used to pattern a polysilicon layer and an underlying gate oxide layer to define gate structures. A thermal oxide step anneals silicon exposed and damaged by this etch. Instead of using this thermal oxide as a blocking layer for a source/drain extension implant, it is removed so as to expose the silicon surfaces of the source/drain regions. A TEOS deposition results in a carbon-bearing silicon dioxide layer in contact with the surfaces of the crystalline source/drain regions. A boron PMOS source/drain extension implant is performed through this carbon-bearing blocking layer. Subsequent steps result in the formation of sidewall spacers, heavily doped source/drain sections, submetal dielectric, an intermetal dielectric interconnect structure, and passivation. The relatively high interstitial recombination rate of the carbon-bearing blocking layer attracts a flow of interstitial silicon.