Abstract: An apparatus comprising one or more delay circuits, a shimmer detector circuit, an averaging circuit, and a multiplexer. The delay circuits may be configured to have a delay of one or more frame periods based on the format of the input video signal. The shimmer detector circuit may be configured to (i) determine which pixel locations in the input video signal exhibit the YC-interference noise oscillation pattern based on the input signal and the output of the delay circuits and (ii) generate a control signal in response to the output of the delays circuits and the input signal. The averaging circuit may be configured to calculate an average of the input signal and the output of the first delay circuit. The multiplexer may be configured to present (i) the input signal when the control signal is in a first state and (ii) the average signal when the control signal is in a second state.