Patents by Inventor Mark E. Thierbach
Mark E. Thierbach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6801995Abstract: A method of assigning unique instruction codes to instructions in an instruction set is disclosed. Such an encoded instruction set is also disclosed. Instructions are grouped according to the particular resources used, where all of the instructions in a group have one or more resource types in common. The position of the highest order active bit in the code is used to identify which resource group a particular instruction belongs to. Instructions in a resource group reserve the same number of bits to identify the specific resources to be used, and no more bits are reserved than required. The remaining unassigned bits are used to encode particular command codes. When such an encoded command is decoded, the resource group is identified by determining the highest order active bit in the instruction. This information is used to determine which bits in the instruction are command bits and which are resource-identifying bits.Type: GrantFiled: August 4, 1998Date of Patent: October 5, 2004Assignee: Agere Systems, Inc.Inventors: Mazhar M. Alidina, Sivanand Simanapalli, Mark E. Thierbach
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Patent number: 6530014Abstract: A near-orthogonal dual-MAC instruction set is provided which implements virtually the entire functionality of the orthogonal instruction set of 272 commands using only 65 commands. The reduced instruction set is achieved by eliminating instructions based on symmetry with respect to the result of the commands and by imposing simple restrictions related to items such as the order of data presentation by the programmer. Specific selections of commands are also determined by the double word aligned memory architecture which is associated with the dual-MAC architecture. The reduced instruction set architecture preserves the functionality and inherent parallelism of the command set and requires fewer command bits to implement than the full orthogonal set.Type: GrantFiled: August 12, 1998Date of Patent: March 4, 2003Assignee: Agere Systems Inc.Inventors: Mazhar M. Alidina, Mark E. Thierbach, Sivanand Simanapalli, Larry R. Tate
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Publication number: 20020099923Abstract: A near-orthogonal dual-MAC instruction set is provided which implements virtually the entire functionality of the orthogonal instruction set of 272 commands using only 65 commands. The reduced instruction set is achieved by eliminating instructions based on symmetry with respect to the result of the commands and by imposing simple restrictions related to items such as the order of data presentation by the programmer. Specific selections of commands are also determined by the double word aligned memory architecture which is associated with the dual-MAC architecture. The reduced instruction set architecture preserves the functionality and inherent parallelism of the command set and requires fewer command bits to implement than the full orthogonal set.Type: ApplicationFiled: August 12, 1998Publication date: July 25, 2002Inventors: MAZHAR M. ALIDINA, SIRVAND SIMANAPALLI, LARRY R. TATE, MARK E. THIERBACH
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Patent number: 5559837Abstract: In accordance with the present invention, a technique for efficiently utilizing memory in determining which next state accumulated cost to retain, such as in a communication system or a Viterbi decoder. The system includes a memory having a portion of registers allocated to a first array and a portion of registers allocated to a second array. The technique includes retrieving a present state accumulated cost from a storage register of the first array and calculating a next state accumulated cost based on the present state accumulated cost. The next state accumulated cost is stored in a storage register of the second array. The second array is designated as containing present state accumulated costs. A present state accumulated cost is retrieved from a storage register of the second array and used in calculating a subsequent next state accumulated cost. The subsequent next state accumulated cost is stored in a storage register of the first array.Type: GrantFiled: June 7, 1995Date of Patent: September 24, 1996Assignee: Lucent Technologies Inc.Inventors: David M. Blaker, Marc S. Diamondstein, Gregory S. Ellard, Mohammad S. Mobin, Homayoon Sam, Mark E. Thierbach
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Patent number: 5465275Abstract: In accordance with the present invention, a technique for efficiently utilizing memory in determining which next state accumulated cost to retain, such as in a communication system or a Viterbi decoder. The system includes a memory having a portion of registers allocated to a first array and a portion of registers allocated to a second array. The technique includes retrieving a present state accumulated cost from a storage register of the first array and calculating a next state accumulated cost based on the present state accumulated cost. The next state accumulated cost is stored in a storage register of the second array. The second array is designated as containing present state accumulated costs. A present state accumulated cost is retrieved from a storage register of the second array and used in calculating a subsequent next state accumulated cost. The subsequent next state accumulated cost is stored in a storage register of the first array.Type: GrantFiled: November 16, 1993Date of Patent: November 7, 1995Assignee: AT&T IPM Corp.Inventors: David M. Blaker, Marc S. Diamondstein, Gregory S. Ellard, Mohammad S. Mobin, Homayoon Sam, Mark E. Thierbach
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Patent number: 5454014Abstract: A signal processor with an embedded Viterbi co-processor is disclosed. The Viterbi branch metric unit contains embedded metric units which calculate either Euclidean or Manhattan metrics for MLSE or deconvolution operations.Type: GrantFiled: November 16, 1993Date of Patent: September 26, 1995Assignee: AT&T Corp.Inventors: David M. Blaker, Gregory S. Ellard, Mohammad S. Mobin, Mark E. Thierbach
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Patent number: 5432804Abstract: An integrated circuit includes a digital signal processor (DSP) and an error correction co-processor (ECCP) that implements a Viterbi decoding function. The DSP and ECCP share a block of multi-port memory, typically by bus multiplexing a dual-port RAM. When the ECCP possesses the RAM, it inhibits the DSP from accessing that block of the RAM by asserting an EBUSY flag. This technique conserves and optimizes the RAM usage, allowing the DSP and ECCP to advantageously be formed on the same integrated circuit chip.Type: GrantFiled: November 16, 1993Date of Patent: July 11, 1995Assignee: AT&T Corp.Inventors: Marc S. Diamondstein, Homayoon Sam, Mark E. Thierbach
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Patent number: 4661922Abstract: A programmed logic array (PLA) is equipped with a first master-slave shift register on the intermediate wordlines (e.g., W.sub.1, W.sub.2 . . . W.sub.n) between AND and OR planes of the PLA and a second master-slave shift register on the output lines emanating from the OR plane. In this way, since the propagation delays of both AND and OR planes are much larger than those of the registers, the speed of operation of the PLA is limited to the greater of the propagation delays of the AND and OR plane instead of the sum of these delays as in prior art.Type: GrantFiled: December 8, 1982Date of Patent: April 28, 1987Assignee: American Telephone and Telegraph CompanyInventor: Mark E. Thierbach
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Patent number: 4493029Abstract: A microprocessor includes a programmable logic array (PLA) adapted to allow "subroutines" or sequences within the PLA. The subroutines can be used by more than one opcode with a return performed to the opcode after execution of the subroutine.Type: GrantFiled: May 14, 1982Date of Patent: January 8, 1985Assignee: AT&T Bell LaboratoriesInventor: Mark E. Thierbach
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Patent number: 4399516Abstract: A hierarchical organization of programmable logic arrays permits the control of microprocessor functions to be achieved in a way which allows otherwise wasted clock time to be used. The mostly independent operations of the several PLA's is organized by "handshake" signals from the latches of one PLA to those of another via AND circuits operative to selectively enable clock signals, in some instances, and data in other instances, to be applied to the latches. The use of the AND circuits enables requisite operations to be achieved with relatively small PLA's.Type: GrantFiled: February 10, 1981Date of Patent: August 16, 1983Assignee: Bell Telephone Laboratories, IncorporatedInventors: Donald E. Blahut, Marc L. Harrison, Michael J. Killian, Mark E. Thierbach
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Patent number: RE32858Abstract: A hierarchical organization of programmable logic arrays permits the control of microprocessor functions to be achieved in a way which allows otherwise wasted clock time to be used. The mostly independent operations of the several PLA's is organized by "handshake" signals from the latches of one PLA to those of another via AND circuits operative to selectively enable clock signals, in some instances, and data in other instances, to be applied to the latches. The use of the AND circuits enables requisite operations to be achieved with relatively small PLA's.Type: GrantFiled: August 16, 1985Date of Patent: February 7, 1989Assignee: American Telephone and Telegraph Company, AT&T Bell LaboratoriesInventors: Donald E. Blahut, Marc L. Harrison, Mark E. Thierbach