Patents by Inventor Mark Eriksson

Mark Eriksson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11133388
    Abstract: Semiconductor heterostructures, methods of making the heterostructures, and quantum dots and quantum computation devices based on the heterostructures are provided. The heterostructures include a quantum well of strained silicon seeded with a relatively low concentration of germanium impurities disposed between two quantum barriers of germanium or a silicon-germanium alloy. The quantum wells are characterized in that the germanium concentration in the wells has an oscillating profile that increases the valley splitting in the conduction band of the silicon quantum well.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: September 28, 2021
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Robert J. Joynt, Mark G. Friesen, Mark A. Eriksson, Susan Nan Coppersmith, Donald E. Savage
  • Patent number: 10572814
    Abstract: A quantum computing system and method for performing quantum computation is provided. In some aspects, the system includes at least one charge qubit comprising a quantum dot assembly prepared with a symmetric charge distribution, wherein the symmetric charge distribution is configured to reduce a coupling between the charge qubit and a charge noise source. The system also includes a controller for controlling the at least one charge qubit to perform a quantum computation. The system further includes an output for providing a report generated using information obtained from the quantum computation performed.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: February 25, 2020
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Mark Friesen, Mark Eriksson, Susan Coppersmith
  • Patent number: 9842921
    Abstract: A quantum semiconductor device is provided. The quantum semiconductor device includes a quantum heterostructure, a dielectric layer, and an electrode. The quantum heterostructure includes a quantum well layer that includes a first 2DEG region, a second 2DEG region, and a third 2DEG region. A first tunnel barrier exists between the first 2DEG region and the second 2DEG region. A second tunnel barrier exists between the second 2DEG region and the third 2DEG region. A third tunnel barrier exists either between the first 2DEG region and the third 2DEG region. The dielectric layer is formed on the quantum heterostructure. The electrode is formed on the dielectric layer directly above the first tunnel barrier.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: December 12, 2017
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Mark A. Eriksson, John King Gamble, Daniel R. Ward, Susan Nan Coppersmith, Mark G. Friesen
  • Publication number: 20170206461
    Abstract: A quantum computing system and method for performing quantum computation is provided. In some aspects, the system includes at least one charge qubit comprising a quantum dot assembly prepared with a symmetric charge distribution, wherein the symmetric charge distribution is configured to reduce a coupling between the charge qubit and a charge noise source. The system also includes a controller for controlling the at least one charge qubit to perform a quantum computation. The system further includes an output for providing a report generated using information obtained from the quantum computation performed.
    Type: Application
    Filed: January 15, 2016
    Publication date: July 20, 2017
    Inventors: Mark Friesen, Mark Eriksson, Susan Coppersmith
  • Publication number: 20150279981
    Abstract: A quantum semiconductor device is provided. The quantum semiconductor device includes a quantum heterostructure, a dielectric layer, and an electrode. The quantum heterostructure includes a quantum well layer that includes a first 2DEG region, a second 2DEG region, and a third 2DEG region. A first tunnel barrier exists between the first 2DEG region and the second 2DEG region. A second tunnel barrier exists between the second 2DEG region and the third 2DEG region. A third tunnel barrier exists either between the first 2DEG region and the third 2DEG region. The dielectric layer is formed on the quantum heterostructure. The electrode is formed on the dielectric layer directly above the first tunnel barrier.
    Type: Application
    Filed: March 12, 2014
    Publication date: October 1, 2015
    Inventors: Mark A. Eriksson, John King Gamble, Daniel R. Ward, Susan Nan Coppersmith, Mark G. Friesen
  • Patent number: 8089073
    Abstract: This invention provides thin film devices that have been processed on their front- and backside. The devices include an active layer that is sufficiently thin to be mechanically flexible. Examples of the devices include back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: January 3, 2012
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Paul G. Evans, Max G. Lagally, Zhenqiang Ma, Hao-Chih Yuan, Guogong Wang, Mark A. Eriksson
  • Publication number: 20100327355
    Abstract: This invention provides thin film devices that have been processed on their front- and backside. The devices include an active layer that is sufficiently thin to be mechanically flexible. Examples of the devices include back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.
    Type: Application
    Filed: September 8, 2010
    Publication date: December 30, 2010
    Inventors: Hao-Chih Yuan, Guogong Wang, Mark A. Eriksson, Paul G. Evans, Max G. Lagally, Zhenqiang Ma
  • Patent number: 7812353
    Abstract: This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: October 12, 2010
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Hao-Chih Yuan, Guogong Wang, Mark A. Eriksson, Paul G. Evans, Max G. Lagally, Zhenqiang Ma
  • Patent number: 7776642
    Abstract: A quantum-well photoelectric device, such as a quantum cascade laser, is constructed of monocrystalline nanoscale membranes physically removed from a substrate and mechanically assembled into a stack.
    Type: Grant
    Filed: May 15, 2008
    Date of Patent: August 17, 2010
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Mark A. Eriksson, Max G. Lagally, Arnold Melvin Kiefer
  • Patent number: 7645933
    Abstract: Carbon nanotube Schottky barrier photovoltaic cells and methods and apparatus for making the cells are provided. The photovoltaic cells include at least one contact made from a first contact material, at least one contact made from a second contact material and a plurality of photoconducting carbon nanotubes bridging the contacts. A Schottky barrier is formed at the interface between the first contact material and the carbon nanotubes while at the interface between the second contact material and the carbon nanotubes, a Schottky barrier for the opposite carrier is formed, or a small, or no Schottky barrier is formed. It is the Schottky barrier asymmetry that allows the photo-excited electron-hole pairs to escape from the carbon nanotube device.
    Type: Grant
    Filed: March 2, 2005
    Date of Patent: January 12, 2010
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Todd R. Narkis, Matt S. Marcus, Max G. Lagally, Mark A. Eriksson
  • Publication number: 20090283749
    Abstract: A quantum-well photoelectric device, such as a quantum cascade laser, is constructed of monocrystalline nanoscale membranes physically removed from a substrate and mechanically assembled into a stack.
    Type: Application
    Filed: May 15, 2008
    Publication date: November 19, 2009
    Inventors: Mark A. Eriksson, Max G. Lagally, Arnold Melvin Kiefer
  • Publication number: 20080315253
    Abstract: This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.
    Type: Application
    Filed: March 4, 2008
    Publication date: December 25, 2008
    Inventors: Hao-Chih Yuan, Guogong Wang, Mark A. Eriksson, Paul G. Evans, Max G. Lagally, Zhenqiang Ma
  • Patent number: 7354809
    Abstract: This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.
    Type: Grant
    Filed: February 13, 2006
    Date of Patent: April 8, 2008
    Assignee: Wisconsin Alumi Research Foundation
    Inventors: Hao-Chih Yuan, Guogong Wang, Mark A. Eriksson, Paul G. Evans, Max G. Lagally, Zhenqiang Ma
  • Publication number: 20070187719
    Abstract: This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.
    Type: Application
    Filed: February 13, 2006
    Publication date: August 16, 2007
    Inventors: Hao-Chih Yuan, Guogong Wang, Mark Eriksson, Paul Evans, Max Lagally, Zhenqiang Ma
  • Patent number: 7135697
    Abstract: A semiconductor quantum dot device converts spin information to charge information utilizing an elongated quantum dot having an asymmetric confining potential along its length so that charge movement occurs during orbital excitation. A single electron sensitive electrometer is utilized to detect the charge movement. Initialization and readout can be carried out rapidly utilizing RF fields at appropriate frequencies.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: November 14, 2006
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Mark Gregory Friesen, Charles George Tahan, Robert James Joynt, Mark A. Eriksson
  • Publication number: 20060196537
    Abstract: Carbon nanotube Schottky barrier photovoltaic cells and methods and apparatus for making the cells are provided. The photovoltaic cells include at least one contact made from a first contact material, at least one contact made from a second contact material and a plurality of photoconducting carbon nanotubes bridging the contacts. A Schottky barrier is formed at the interface between the first contact material and the carbon nanotubes while at the interface between the second contact material and the carbon nanotubes, a Schottky barrier for the opposite carrier is formed, or a small, or no Schottky barrier is formed. It is the Schottky barrier asymmetry that allows the photo-excited electron-hole pairs to escape from the carbon nanotube device.
    Type: Application
    Filed: March 2, 2005
    Publication date: September 7, 2006
    Inventors: Todd Narkis, Matt Marcus, Max Lagally, Mark Eriksson
  • Publication number: 20060027275
    Abstract: A block for a modular fluid block assembly is disclosed. The block includes first and second opposed faces and first and second apertures from the first face to the second face for receiving a fastener. Each aperture includes a first end and a second end and a head receiving cavity disposed adjacent the first end. The block further includes a fluidic passage passing from the first face to the second face and a pair of fastener receiver cavities in the first face. The block further includes a pair of head receiving cavities in the second face.
    Type: Application
    Filed: October 3, 2005
    Publication date: February 9, 2006
    Inventors: Mark Eriksson, Jeffry Markulec, Dennis Rex
  • Publication number: 20050184285
    Abstract: A semiconductor quantum dot device converts spin information to charge information utilizing an elongated quantum dot having an asymmetric confining potential along its length so that charge movement occurs during orbital excitation. A single electron sensitive electrometer is utilized to detect the charge movement. Initialization and readout can be carried out rapidly utilizing RF fields at appropriate frequencies.
    Type: Application
    Filed: February 25, 2004
    Publication date: August 25, 2005
    Inventors: Mark Friesen, Charles Tahan, Robert Joynt, Mark Eriksson
  • Patent number: 6597010
    Abstract: Semiconductor dot devices include a multiple layer semiconductor structure having a substrate, a back gate electrode layer, a quantum well layer, a tunnel barrier layer between the quantum well layer and the back gate, and a barrier layer above the quantum well layer. Multiple electrode gates are formed on the multi-layer semiconductor with the gates spaced from each other by a region beneath which quantum dots may be defined. Appropriate voltages applied to the electrodes allow the development and appropriate positioning of the quantum dots, allowing a large number of quantum dots be formed in a series with appropriate coupling between the dots.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: July 22, 2003
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Mark A. Eriksson, Mark G. Friesen, Robert J. Joynt, Max G. Lagally, Daniel W. van der Weide, Paul Rugheimer, Donald E. Savage
  • Publication number: 20020179897
    Abstract: Semiconductor dot devices include a multiple layer semiconductor structure having a substrate, a back gate electrode layer, a quantum well layer, a tunnel barrier layer between the quantum well layer and the back gate, and a barrier layer above the quantum well layer. Multiple electrode gates are formed on the multi-layer semiconductor with the gates spaced from each other by a region beneath which quantum dots may be defined. Appropriate voltages applied to the electrodes allow the development and appropriate positioning of the quantum dots, allowing a large number of quantum dots be formed in a series with appropriate coupling between the dots.
    Type: Application
    Filed: March 8, 2002
    Publication date: December 5, 2002
    Inventors: Mark A. Eriksson, Mark G. Friesen, Robert J. Joynt, Max G. Lagally, Daniel W. van der Weide, Paul Rugheimer, Donald E. Savage