Abstract: An integrated circuit comprises a transistor extending into a semiconductor substrate and having a gate structure having major and minor axes parallel to a surface of the semiconductor substrate, and a UV-opaque sheet structure vertically spaced apart from a top surface of the gate structure by a first distance and including an opening, the opening having first and second sides about parallel to the major axis, at least one of the first and second sides laterally spaced apart from a corresponding side of the gate structure by a second distance that is less than or equal to the first distance.

Abstract: An atmometer system based on an analog floating-gate structure and circuit. The floating-gate circuit includes a floating-gate electrode that serves as a gate electrode for a transistor and a plate of a storage capacitor. A conductor element exposed at the surface of the integrated circuit is electrically connected to the floating-gate electrode; reference conductor elements biased to ground are also at the surface of the integrated circuit. In operation, the transistor is biased and moisture is dispensed at the surface. The drain current of the transistor changes as the floating-gate electrode discharges via the surface conductors and a conduction path presented by the moisture. The elapsed time until the drain current stabilizes indicates the evaporation rate.

Abstract: An analog floating-gate (AFG) inclinometer where a plurality of AFG sensors are provided to detect the presence of a discharge caused by settling of a conductive liquid droplet contained in a sealed microchannel under gravity. A plurality of sensor port electrodes associated with the AFG sensors are placed along the length of a curved sealed microchannel of the inclinometer at specific positions calibrated to corresponding angular inclinations. Discharge detected at a specific AFG sensor port during measurement due to the movement of the conductive liquid droplet under gravity is used in determining a surface inclination being measured.

Abstract: An atmometer system based on an analog floating-gate structure and circuit. The floating-gate circuit includes a floating-gate electrode that serves as a gate electrode for a transistor and a plate of a storage capacitor. A conductor element exposed at the surface of the integrated circuit is electrically connected to the floating-gate electrode; reference conductor elements biased to ground are also at the surface of the integrated circuit. In operation, the transistor is biased and moisture is dispensed at the surface. The drain current of the transistor changes as the floating-gate electrode discharges via the surface conductors and a conduction path presented by the moisture. The elapsed time until the drain current stabilizes indicates the evaporation rate.

Abstract: An analog floating-gate (AFG) inclinometer where a plurality of AFG sensors are provided to detect the presence of a discharge caused by settling of a conductive liquid droplet contained in a sealed microchannel under gravity. A plurality of sensor port electrodes associated with the AFG sensors are placed along the length of a curved sealed microchannel of the inclinometer at specific positions calibrated to corresponding angular inclinations. Discharge detected at a specific AFG sensor port during measurement due to the movement of the conductive liquid droplet under gravity is used in determining a surface inclination being measured.

Abstract: An atmometer system based on an analog floating-gate structure and circuit. The floating-gate circuit includes a floating-gate electrode that serves as a gate electrode for a transistor and a plate of a storage capacitor. A conductor element exposed at the surface of the integrated circuit is electrically connected to the floating-gate electrode; reference conductor elements biased to ground are also at the surface of the integrated circuit. In operation, the transistor is biased and moisture is dispensed at the surface. The drain current of the transistor changes as the floating-gate electrode discharges via the surface conductors and a conduction path presented by the moisture. The elapsed time until the drain current stabilizes indicates the evaporation rate.

Abstract: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.

Abstract: An atmometer system based on an analog floating-gate structure and circuit. The floating-gate circuit includes a floating-gate electrode that serves as a gate electrode for a transistor and a plate of a storage capacitor. A conductor element exposed at the surface of the integrated circuit is electrically connected to the floating-gate electrode; reference conductor elements biased to ground are also at the surface of the integrated circuit. In operation, the transistor is biased and moisture is dispensed at the surface. The drain current of the transistor changes as the floating-gate electrode discharges via the surface conductors and a conduction path presented by the moisture. The elapsed time until the drain current stabilizes indicates the evaporation rate.

Abstract: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.

Abstract: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.

Abstract: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.

Abstract: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.

Abstract: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.