Patents by Inventor Mark Essert

Mark Essert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240304538
    Abstract: A power semiconductor module arrangement includes: a substrate having a dielectric insulation layer and a first metallization layer arranged on a first surface of the dielectric insulation layer; at least one semiconductor body arranged on and attached to the first metallization layer by an electrically conductive connection layer; and at least one electrically conducting element arranged on the first metallization layer. The first metallization layer is a structured layer having a plurality of different sub-sections. The first metallization layer has a uniform thickness in a vertical direction, the vertical direction being perpendicular to the first surface of the dielectric insulation layer. Each electrically conducting element is arranged on and covers a subarea of a sub-section, thereby increasing a cross-sectional area of the subarea of the respective sub-section. Each electrically conducting element includes an electrically conductive connection layer without a semiconductor body arranged thereon.
    Type: Application
    Filed: February 29, 2024
    Publication date: September 12, 2024
    Inventors: Christoph Bayer, Matthias Bürger, Ulrich Nolten, Mark Essert
  • Patent number: 10092974
    Abstract: One aspect of the invention relates to a method for producing a circuit carrier. For this purpose, an electrically insulating carrier is provided, having an upper side and also an underside opposite from the upper side. A first metal foil and a hardening material are likewise provided. Then, an upper metallization layer, which is arranged on the upper side and has a hardening area, is produced. In this case, at least one contiguous portion of the hardening area is created by at least part of the hardening material being diffused into the first metal foil.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: October 9, 2018
    Assignee: Infineon Technologies AG
    Inventors: Mark Essert, Marianna Nomann, Thomas Nuebel, Guido Strotmann
  • Publication number: 20160001393
    Abstract: One aspect of the invention relates to a method for producing a circuit carrier. For this purpose, an electrically insulating carrier is provided, having an upper side and also an underside opposite from the upper side. A first metal foil and a hardening material are likewise provided. Then, an upper metallization layer, which is arranged on the upper side and has a hardening area, is produced. In this case, at least one contiguous portion of the hardening area is created by at least part of the hardening material being diffused into the first metal foil.
    Type: Application
    Filed: June 26, 2015
    Publication date: January 7, 2016
    Inventors: Mark Essert, Marianna Nomann, Thomas Nuebel, Guido Strotmann
  • Patent number: 9000580
    Abstract: A power semiconductor module includes a baseplate having a top side, an underside, and a depression formed in the baseplate. The depression extends into the baseplate proceeding from the top side. A thickness of the baseplate is locally reduced in a region of the depression. The power semiconductor module further includes a circuit carrier arranged above the depression on the top side of the baseplate such that the depression is interposed between the circuit carrier and the underside of the baseplate.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: April 7, 2015
    Assignee: Infineon Technologies AG
    Inventors: Torsten Groening, Mark Essert, Christian Steininger, Roman Lennart Tschirbs
  • Patent number: 8134838
    Abstract: A semiconductor module and a method. One embodiment provides a housing with a housing frame and a pluggable carrier which is plugged in the housing frame. The pluggable carrier is equipped with a lead which includes an internal portion which is arranged inside the housing, and an external portion which is arranged outside the housing. The internal portion is electrically coupled to an electric component of the power semiconductor module. The external portion allows for electrically coupling the power semiconductor module.
    Type: Grant
    Filed: July 21, 2008
    Date of Patent: March 13, 2012
    Assignee: Infineon Technologies AG
    Inventors: Mark Essert, Martin Knecht, Alexander Ciliox
  • Publication number: 20100014269
    Abstract: A semiconductor module and a method. One embodiment provides a housing with a housing frame and a pluggable carrier which is plugged in the housing frame. The pluggable carrier is equipped with a lead which includes an internal portion which is arranged inside the housing, and an external portion which is arranged outside the housing. The internal portion is electrically coupled to an electric component of the power semiconductor module. The external portion allows for electrically coupling the power semiconductor module.
    Type: Application
    Filed: July 21, 2008
    Publication date: January 21, 2010
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Mark Essert, Martin Knecht, Alexander Ciliox
  • Patent number: 7494389
    Abstract: According to an embodiment, a press-fit connector includes a first part with a first end and with a second end, and a second part with a first end and with a second end. The second end of the first part is electrically and mechanically joined to the first end of the second part. The first part is made of a first material with a first mechanical strength. The second part is made of a second material with a second mechanical strength. The first mechanical strength is greater than the second mechanical strength.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: February 24, 2009
    Assignee: Infineon Technologies AG
    Inventors: Mark Essert, Martin Knecht, Alexander Ciliox