Patents by Inventor Mark F. Deherrera
Mark F. Deherrera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7447060Abstract: According to an example embodiment, a method (500) includes applying a magnetic field to an array of Magnetic Tunnel Junction (MTJ) bits, a magnitude of the magnetic field sufficient to eliminate a stuck-at-mid condition exhibited by one of the MTJ bits without causing other ones of the MTJ bits to develop the stuck-at-mid condition.Type: GrantFiled: February 23, 2007Date of Patent: November 4, 2008Assignee: Everspin Technologies, Inc.Inventors: Eric John Salter, Mark F. Deherrera, Thomas H. Lee
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Publication number: 20080205122Abstract: According to an example embodiment, a method (500) includes applying a magnetic field to an array of Magnetic Tunnel Junction (MTJ) bits, a magnitude of the magnetic field sufficient to eliminate a stuck-at-mid condition exhibited by one of the MTJ bits without causing other ones of the MTJ bits to develop the stuck-at-mid condition.Type: ApplicationFiled: February 23, 2007Publication date: August 28, 2008Inventors: Eric J. Salter, Mark F. Deherrera, Thomas H. Lee
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Patent number: 7184300Abstract: A method to switch a scalable magnetoresistive memory cell including the steps of providing a magnetoresistive memory device sandwiched between a word line and a digit line so that current waveforms can be applied to the word and digit lines at various times to cause a magnetic field flux to rotate the effective magnetic moment vector of the device by approximately 180°. The magnetoresistive memory device includes N ferromagnetic layers that are anti-ferromagnetically coupled. N can be adjusted to change the magnetic switching volume of the device.Type: GrantFiled: January 9, 2003Date of Patent: February 27, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Anatoli Korkin, legal representative, Bradley N. Engel, Nicholas D. Rizzo, Mark F. Deherrera, Jason Allen Janesky, Leonid Savtchenko, deceased
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Patent number: 7158407Abstract: A method is provided for testing magnetic bits (3, 104, 514) of an array. A train of first (702), second (704), and third (706) pulses is provided to a desired bit, the first and second pulses beginning at a substantially similar low field and increasing in similar amounts with respect to successive trains of the first, second, and third pulses, the third pulse having a current amplitude sufficient to toggle the magnetic bit. A representative count is recorded in response to switching of the bit. The above steps are repeated and a determination is made of the current amplitude required to write and toggle the bit.Type: GrantFiled: April 29, 2005Date of Patent: January 2, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Nicholas D. Rizzo, Mark F. Deherrera, Jason A. Janesky
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Patent number: 7105363Abstract: A method for fabricating a cladded conductor (42) for use in a magnetoelectronics device is provided. The method includes providing a substrate (10) and forming a conductive barrier layer (12) overlying the substrate (10). A dielectric layer (16) is formed overlying the conductive barrier layer (12) and a conducting line (20) is formed within a portion of the dielectric layer (16). The dielectric layer (16) is removed and a flux concentrator (30) is formed overlying the conducting line (20).Type: GrantFiled: March 16, 2005Date of Patent: September 12, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Mark A. Durlam, Jeffrey H. Baker, Brian R. Butcher, Mark F. Deherrera, John J. D'Urso, Earl D. Fuchs, Gregory W. Grynkewich, Kelly W. Kyler, Jaynal A. Molla, J. Jack Ren, Nicholas D. Rizzo
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Patent number: 7088608Abstract: A reduced power method of writing MRAM bits is disclosed. The reduced power method includes writing MRAM bits by applying a first magnetic field having a low magnitude, then determining if the bit has switched. If not, a second magnetic field having a higher magnitude is applied. Applying magnetic fields to an MRAM bit cell is accomplished by sending a current pulse through a strip line adjacent to the MRAM bit cell. The technique can be performed for every write to an MRAM bit. Alternatively, the weaker magnetic field can be applied during system test or system initialization, and if the weaker field fails to write the bit to a desired value, the failing result is stored and each subsequent write to the MRAM bit utilizes the stronger magnetic field.Type: GrantFiled: December 16, 2003Date of Patent: August 8, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Mark F. DeHerrera, Bengt Johan Akerman
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Patent number: 6956763Abstract: A direct write is provided for a magnetoelectronics information device that includes producing a first magnetic field with a first field magnitude in proximity to the magnetoelectronics information device at a first time (t1). Once this first magnetic field with the first magnitude is produced, a second magnetic field with a second field magnitude is produced in proximity to the magnetoelectronics information device at a second time (t2). The first magnetic field is adjusted to provide a third magnitude at a third time (t3) that is less than the first field magnitude and greater than zero, and the second magnetic field is adjusted to provide a fourth field magnitude at a fourth time (t4) that is less than the second field magnitude. This direct write is used in conjunction with other direct writes and also in combination with toggle writes to write the MRAM element without an initial read.Type: GrantFiled: June 27, 2003Date of Patent: October 18, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Bengt J. Akerman, Mark F. Deherrera, Bradley N. Engel, Nicholas D. Rizzo
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Patent number: 6909631Abstract: An MRAM is provided that minimizes the limits in MRAM density imposed by utilization of an isolation or select device in each memory cell. In addition, methods are provided for reading an MTJ in a ganged memory cell of the MRAM. The method includes determining an electrical value that is at least partially associated with a resistance of a ganged memory cell of the MRAM. The MTJ in the ganged memory cell is toggled and a second electrical value, which is at least partially associated with the resistance of the ganged memory cell, is determined after toggling the MTJ. Once the electrical value prior to the toggling and after the toggling is determined, the difference between the two electrical values is analyzed to determine the value of the MTJ.Type: GrantFiled: October 2, 2003Date of Patent: June 21, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Mark A. Durlam, Thomas W. Andre, Mark F. DeHerrera, Bradley N. Engel, Bradley J. Garni, Joseph J. Nahas, Nicholas D. Rizzo, Saied Tehrani
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Patent number: 6888743Abstract: An MRAM architecture is provided that reduces the number of isolation transistors. The MRAM architecture includes magnetoresistive memory cells that are electrically coupled to form a ganged memory cell. The magnetoresistive memory cells of the ganged memory cell are formed with Magnetic Tunnel Junctions (MTJs) and formed without isolation devices, such as isolation transistors, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells. Preferably, the magnetoresistive memory cells of the ganged memory cell only include MTJs, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells.Type: GrantFiled: December 27, 2002Date of Patent: May 3, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Mark A. Durlam, Thomas W. Andre, Brian R. Butcher, Mark F. Deherrera, Bradley N. Engel, Bradley J. Garni, Gregory W. Grynkewich, Joseph J. Nahas, Nicholas D. Rizzo, Saied Tehrani, Clarance J. Tracy
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Patent number: 6885074Abstract: A method for fabricating a cladded conductor (42) for use in a magnetoelectronics device is provided. The method includes providing a substrate (10) and forming a conductive barrier layer (12) overlying the substrate (10). A dielectric layer (16) is formed overlying the conductive barrier layer (12) and a conducting line (20) is formed within a portion of the dielectric layer (16). The dielectric layer (16) is removed and a flux concentrator (30) is formed overlying the conducting line (20).Type: GrantFiled: November 27, 2002Date of Patent: April 26, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Mark A. Durlam, Jeffrey H. Baker, Brian R. Butcher, Mark F. Deherrera, John J. D'Urso, Earl D. Fuchs, Gregory W. Grynkewich, Kelly W. Kyler, Jaynal A. Molla, J. Jack Ren, Nicholas D. Rizzo
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Publication number: 20040264238Abstract: A direct write is provided for a magnetoelectronics information device that includes producing a first magnetic field with a first field magnitude in proximity to the magnetoelectronics information device at a first time (t1). Once this first magnetic field with the first magnitude is produced, a second magnetic field with a second field magnitude is produced in proximity to the magnetoelectronics information device at a second time (t2). The first magnetic field is adjusted to provide a third magnitude at a third time (t3) that is less than the first field magnitude and greater than zero, and the second magnetic field is adjusted to provide a fourth field magnitude at a fourth time (t4) that is less than the second field magnitude. This direct write is used in conjunction with other direct writes and also in combination with toggle writes to write the MRAM element without an initial read.Type: ApplicationFiled: June 27, 2003Publication date: December 30, 2004Inventors: Bengt J. Akerman, Mark F. Deherrera, Bradley N. Engel, Nicholas D. Rizzo
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Patent number: 6760266Abstract: A sense amplifier (1300, 1500) is provided for sensing the state of a toggling type magnetoresistive random access memory (MRAM) cell without using a reference. The sense amplifier (1300, 1500) employs a sample-and-hold circuit (1336, 1508) combined with a current-to-voltage converter (1301, 1501), gain circuit (1303), and cross-coupled latch (1305, 1503) to sense the state of a bit. The sense amplifier (1300, 1500), first senses and holds a first state of the cell. The cell is toggled to a second state. Then, the sense amplifier (1300, 1500) compares the first state to the second state to determine the first state of a toggling type memory cell.Type: GrantFiled: June 28, 2002Date of Patent: July 6, 2004Assignee: Freescale Semiconductor, Inc.Inventors: Bradley J. Garni, Mark F. Deherrera, Mark A. Durlam, Bradley N. Engel, Thomas W. Andre, Joseph J. Nahas, Chitra K. Subramanian
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Publication number: 20040125646Abstract: An MRAM architecture is provided that reduces the number of isolation transistors. The MRAM architecture includes magnetoresistive memory cells that are electrically coupled to form a ganged memory cell. The magnetoresistive memory cells of the ganged memory cell are formed with Magnetic Tunnel Junctions (MTJs) and formed without isolation devices, such as isolation transistors, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells. Preferably, the magnetoresistive memory cells of the ganged memory cell only include MTJs, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells.Type: ApplicationFiled: December 27, 2002Publication date: July 1, 2004Inventors: Mark A. Durlam, Thomas W. Andre, Brian R. Butcher, Mark F. Deherrera, Bradley N. Engel, Bradley J. Garni, Gregory W. Grynkewich, Joseph J. Nahas, Nicholas D. Rizzo, Saied Tehrani, Clarance J. Tracy
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Publication number: 20040125649Abstract: An MRAM is provided that minimizes the limits in MRAM density imposed by utilization of an isolation or select device in each memory cell. In addition, methods are provided for reading an MTJ in a ganged memory cell of the MRAM. The method includes determining an electrical value that is at least partially associated with a resistance of a ganged memory cell of the MRAM. The MTJ in the ganged memory cell is toggled and a second electrical value, which is at least partially associated with the resistance of the ganged memory cell, is determined after toggling the MTJ. Once the electrical value prior to the toggling and after the toggling is determined, the difference between the two electrical values is analyzed to determine the value of the MTJ.Type: ApplicationFiled: October 2, 2003Publication date: July 1, 2004Inventors: Mark A. Durlam, Thomas W. Andre, Mark F. Deherrera, Bradley N. Engel, Bradley J. Garni, Joseph J. Nahas, Nicholas D. Rizzo, Saied Tehrani
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Publication number: 20040099908Abstract: A method for fabricating a cladded conductor (42) for use in a magnetoelectronics device is provided. The method includes providing a substrate (10) and forming a conductive barrier layer (12) overlying the substrate (10). A dielectric layer (16) is formed overlying the conductive barrier layer (12) and a conducting line (20) is formed within a portion of the dielectric layer (16). The dielectric layer (16) is removed and a flux concentrator (30) is formed overlying the conducting line (20).Type: ApplicationFiled: November 27, 2002Publication date: May 27, 2004Inventors: Mark A. Durlam, Jeffrey H. Baker, Brian R. Butcher, Mark F. Deherrera, John J. D'Urso, Earl D. Fuchs, Gregory W. Grynkewich, Kelly W. Kyler, Jaynal A. Molla, J. Jack Ren, Nicholas D. Rizzo
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Publication number: 20040001383Abstract: A sense amplifier (1300, 1500) is provided for sensing the state of a toggling type magnetoresistive random access memory (MRAM) cell without using a reference. The sense amplifier (1300, 1500) employs a sample-and-hold circuit (1336, 1508) combined with a current-to-voltage converter (1301, 1501), gain circuit (1303), and cross-coupled latch (1305, 1503) to sense the state of a bit. The sense amplifier (1300, 1500), first senses and holds a first state of the cell. The cell is toggled to a second state. Then, the sense amplifier (1300, 1500) compares the first state to the second state to determine the first state of a toggling type memory cell.Type: ApplicationFiled: June 28, 2002Publication date: January 1, 2004Inventors: Bradley J. Garni, Mark F. Deherrera, Mark A. Durlam, Bradley N. Engel, Thomas W. Andre, Joseph J. Nahas, Chitra K. Subramanian
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Publication number: 20030128603Abstract: A method to switch a scalable magnetoresistive memory cell including the steps of providing a magnetoresistive memory device sandwiched between a word line and a digit line so that current waveforms can be applied to the word and digit lines at various times to cause a magnetic field flux to rotate the effective magnetic moment vector of the device by approximately 180°. The magnetoresistive memory device includes N ferromagnetic layers that are anti-ferromagnetically coupled. N can be adjusted to change the magnetic switching volume of the device.Type: ApplicationFiled: January 9, 2003Publication date: July 10, 2003Inventors: Leonid Savtchenko, Anatoli A. Korkin, Bradley N. Engel, Nicholas D. Rizzo, Mark F. Deherrera, Jason Allen Janesky
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Publication number: 20030072174Abstract: A method to switch a scalable magnetoresistive memory cell including the steps of providing a magnetoresistive memory device sandwiched between a word line and a digit line so that current waveforms can be applied to the word and digit lines at various times to cause a magnetic field flux to rotate the effective magnetic moment vector of the device by approximately 180°. The magnetoresistive memory device includes N ferromagnetic layers that are anti-ferromagnetically coupled. N can be adjusted to change the magnetic switching volume of the device.Type: ApplicationFiled: October 16, 2001Publication date: April 17, 2003Inventors: Leonid Savtchenko, Anatoli A. Korkin, Bradley N. Engel, Nicholas D. Rizzo, Mark F. Deherrera, Jason Allen Janesky
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Patent number: 6545906Abstract: A method to switch a scalable magnetoresistive memory cell including the steps of providing a magnetoresistive memory device sandwiched between a word line and a digit line so that current waveforms can be applied to the word and digit lines at various times to cause a magnetic field flux to rotate the effective magnetic moment vector of the device by approximately 180°. The magnetoresistive memory device includes N ferromagnetic layers that are anti-ferromagnetically coupled. N can be adjusted to change the magnetic switching volume of the device.Type: GrantFiled: October 16, 2001Date of Patent: April 8, 2003Assignee: Motorola, Inc.Inventors: Leonid Savtchenko, Bradley N. Engel, Nicholas D. Rizzo, Mark F. Deherrera, Jason Allen Janesky
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Patent number: 6518071Abstract: A method of fabricating a MRAM device with a taper comprising the steps of providing a substrate, forming a dielectric region with positioned on the substrate, patterning and isotropically etching through the dielectric region to the substrate to form a trench, depositing the MRAM device within the trench wherein the MRAM device includes a first ferromagnetic region with a width positioned on the substrate, a non-ferromagnetic spacer layer with a width positioned on the first ferromagnetic region, and a second ferromagnetic region with a width positioned on the non-ferromagnetic spacer layer wherein the taper is formed by making the width of the first ferromagnetic region greater than the width of the non-ferromagnetic spacer layer, and the width of the non-ferromagnetic spacer layer greater than the width of the second ferromagnetic region so that the first ferromagnetic region is separated from the second ferromagnetic region.Type: GrantFiled: March 28, 2002Date of Patent: February 11, 2003Assignee: Motorola, Inc.Inventors: Mark A. Durlam, Mark F. Deherrera, Kelly W. Kyler, Brian R. Butcher, Gregory W. Grynkewich, Steven M. Smith, Charles Snyder, Jon M. Slaughter