Abstract: The problems of meeting tight latency requirement while keeping network design low in cost and complexity are solved by the present invention of a network controller with a transaction logic block and a descriptor memory. The invention allows the data buffers and the buffer descriptors to be located in two physically separate memory subsystems. Data buffers can reside in a main system memory which are shared by other system clients. The buffer descriptors, which typically require significantly less memory space than data buffers, can reside in a special dedicated memory which can be low cost. The invention provides a method to allow buffer descriptors to be located in a low latency memory, which can be local to the network adapter. The data buffers can be located in a system shared memory. This design allows system shared resources, e.g. main system memory or bus, to be designed with relatively longer delay budget.

Abstract: A parser for reading bits of a packet has a set of logic circuits implemented in a computer chip; a memory interacting with the computer chip, the memory providing first data to the set of logic circuits; means for reading bits from any field of packet into the set of logic circuits, the bits providing second data to the set of logic circuits; means, responsive to the first data and the second data, for the logic circuits to interpret bits of the packet.

Abstract: A network adapter with high throughput data transfer circuit to optimize network data transfers, with host receive ring resource monitoring and reporting is disclosed. Time critical network data is transferred between the network adapter and the host computer system by means of a high throughput data transfer circuit. The high throughput data transfer circuit is designed to provide throughput equal to the bandwidth of a high speed local area network such as the Fiber Distributed Data Interconnect. The high throughput data transfer circuit will inform the local intelligence of the network adapter if the network adapter has used up all host computer system memory allocated for storing data received from the network. Adapter management data is transferred between the network adapter and the host computer system local area network through a lower throughput data transfer circuit.

Abstract: A decryption method, and associated cryptographic processor, for performing in-line decryption of information frames received from a communication network through a first in-line processing stage. As an information packet is streamed into the cryptographic processor, a determination is made to an acceptable level of probability whether the packet contains data that should be decrypted. The decision whether or not decrypt is made by analyzing the incoming packet header, recognizing a limited number of packet formats, and further parsing the packet to locate any encrypted data and to make sure that the packet is not a segment of a larger message. Falsely decrypted packets are looped back through the cryptographic processor, to regenerate the data that was falsely decrypted. Decryption and encryption are performed in such a manner that a false decryption is completely reversible without loss of data.

Abstract: A method and corresponding apparatus for encoding and decoding additional status bits into an existing frame status byte transmitted as part of a packet of information in a communication network. The described scheme provides for the encoding and decoding of two additional status bits, without having to modify the packet format. In the disclosed embodiment of the invention, the additional status bits are used to convey information to a node processor concerning decryption processing of a received information packets.

Abstract: A method for selective disclosure of the identity of a communication protocol under which an information packet originated, but without incorrectly identifying the protocol in a header accompanying the packet. If there is a need to conceal the identity of the underlying source protocol, a special anonymous protocol identifier is used, instead of the real protocol identifier, in the header of an encrypted information packet. Network monitors can then still provide accurate information concerning traffic on the network, without having this information distorted by the use of incorrect communication protocols. If there is a desire to reveal the underlying protocol, a subnetwork protocol frame format is used to store the protocol identity and signify whether the packet is encrypted. A packet that is of a non-subnetwork protocol can be encapsulated with a subnetwork header containing a special code signifying that there is an encapsulated packet and containing the original protocol identifier.

Abstract: An output controller in a repeater node for controlling data transfers in a data communication system in which each node is operated by an independent local clock. Nodes will occasionally delete idle bytes from a preamble to recenter an elasticity buffer. The output controller performs a process that requires the elasticity buffer to be progressively more full before deleting another idle byte from the preamble. Transmission of the start of a subsequent frame is delayed and additional idle bytes are transmitted when the number of idle bytes being transmitted is at or below a certain threshold. Multiple thresholds are utilized so that the amount of the delay can be adjusted.

Abstract: The present system includes logic circuitry to be connected between at least two networks. When a message is sent by a station in a first network, the destination part of the message will be examined by the logic circuitry to see if the destination address has been recorded (stored) and if so to what network the destination station belongs. If the destination address is located in the sending network, the message is not sent to the non-sending network. If the destination address is located in the non-sending network, the message will be sent thereto. If the destination address is not recorded, i.e., it represents a new station, the message will be sent to the non-sending network (such a message is automatically sent to its own network). In the latter case when such a new station becomes a source station, its address will be recorded so that the next time such a station is a destination, the system will know in which network it is located.

Abstract: Interface apparatus which facilitates asynchronous parallel transfer of data at a speed of up to at least 1.6 megabits per second between a minicomputer and a microcomputer. The apparatus includes a plurality of bidirectional data circuits parallel coupled between the minicomputer and the microcomputer for carrying data between the minicomputer and the microcomputer when either computer wants to send data to the other computer.

Abstract: The digital bus is an asynchronous, linear, open-ended digital bus which is coupled to two or more computer/controllers. The bus includes address control circuit lines comprising a bus busy line used by a controller to assert a bus busy signal thereon to gain control of the bus, and to determine if another computer/controller is using the bus, a receiver computer/controller request line used by a controller for requesting permission to send data to another controller, and a receiver computer/controller ready line used by a controller for indicating that that controller is ready to receive data. Data control circuit lines are also provided comprising a data ready line used by a controller for placing a ready-to-send-data signal thereon and a data accept line used by a controller for placing a ready-to-accept-data signal thereon. Also, address bus circuit lines are provided comprising five binary address lines used by a controller for placing an address thereon, which address can have up to five bits.