Patents by Inventor Mark Fairhurst
Mark Fairhurst has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10686714Abstract: In the subject system for a network switch may receive one or more packets via a set of input ports. The network switch may write the one or more packets into an ingress buffer of an ingress tile shared by the set of input ports. The network switch may read the one or more packets from the ingress buffer according to a schedule by a scheduler. The network switch may forward the read one or more packets to a plurality of output ports.Type: GrantFiled: April 27, 2018Date of Patent: June 16, 2020Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventors: Mark Fairhurst, Eugene N. Opsasnick, Michael H. Lau, Ari Aravinthan, Manoj Lakshmygopalakrishnan, Ankit Sajjan Kumar Bansal, Yehuda Avidan, Noam Halevy
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Patent number: 10567307Abstract: In the subject system for a network switch may determine to transition the output port of the network switch between a store-and-forward (SAF) state and a cut-through (CT) state based on at least one factor. The network switch may determine, based on a condition of the output port, whether to transition the output port to a transition-cut-through (TCT) state or directly to a CT state when transitioning the output port to the CT state. When the output port is transitioned to the TCT state, the network switch may determine, based on the condition of the output port, whether to transition the output port to the CT state or to transition the output port back to the SAF state.Type: GrantFiled: April 27, 2018Date of Patent: February 18, 2020Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventors: Mark Fairhurst, Eugene N. Opsasnick, Michael H. Lau, Ari Aravinthan, Manoj Lakshmygopalakrishnan, Ankit Sajjan Kumar Bansal, Yehuda Avidan, Noam Halevy
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Publication number: 20190334828Abstract: In the subject system for a network switch may receive one or more packets via a set of input ports. The network switch may write the one or more packets into an ingress buffer of an ingress tile shared by the set of input ports. The network switch may read the one or more packets from the ingress buffer according to a schedule by a scheduler. The network switch may forward the read one or more packets to a plurality of output ports.Type: ApplicationFiled: April 27, 2018Publication date: October 31, 2019Inventors: Mark FAIRHURST, Eugene N. OPSASNICK, Michael H. LAU, Ari ARAVINTHAN, Manoj LAKSHMYGOPALAKRISHNAN, Ankit Sajjan Kumar BANSAL, Yehuda AVIDAN, Noam HALEVY
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Publication number: 20190334837Abstract: In the subject system for a network switch may determine to transition the output port of the network switch between a store-and-forward (SAF) state and a cut-through (CT) state based on at least one factor. The network switch may determine, based on a condition of the output port, whether to transition the output port to a transition-cut-through (TCT) state or directly to a CT state when transitioning the output port to the CT state. When the output port is transitioned to the TCT state, the network switch may determine, based on the condition of the output port, whether to transition the output port to the CT state or to transition the output port back to the SAF state.Type: ApplicationFiled: April 27, 2018Publication date: October 31, 2019Inventors: Mark FAIRHURST, Eugene N. OPSASNICK, Michael H. LAU, Ari ARAVINTHAN, Manoj LAKSHMYGOPALAKRISHNAN, Ankit Sajjan Kumar BANSAL, Yehuda AVIDAN, Noam HALEVY
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Publication number: 20170025165Abstract: Memory systems, such as SRAM systems, are described that comprise a series of adjacently placed memory components for providing memory data and memory transaction information from one component to another. Input pins are strategically placed, and muxing and ancillary logic are included within memory components, to allow for the adjacent placement. The memory data and memory transaction information are provided by a memory component in a configurable feedthrough or pipelined manner based on the period of an operating clock. The memory data and memory transaction information are received by a memory system at only a first memory component in the series, and are provided from the memory system by only a last memory component in the series. Memory components selectively provide to subsequent memory components in the series either locally stored data, or data received by the memory components as an input.Type: ApplicationFiled: July 31, 2015Publication date: January 26, 2017Inventors: Mark Fairhurst, Travis R. Hebig
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Patent number: 8155134Abstract: A Queue Manager (QM) system and method are provided for communicating control messages between processors. The method accepts control messages from a source processor addressed to a destination processor. The control messages are loaded in a first-in first-out (FIFO) queue associated with the destination processor. Then, the method serially supplies loaded control messages to the destination processor from the queue. The messages may be accepted from a plurality of source processors addressed to the same destination processor. The control messages are added to the queue in the order in which they are received. In one aspect, a plurality of parallel FIFO queues may be established that are associated with the same destination processor. Then, the method differentiates the control messages into the parallel FIFO queues and supplies control messages from the parallel FIFO queues in an order responsive to criteria such as queue ranking, weighting, or shaping.Type: GrantFiled: September 29, 2007Date of Patent: April 10, 2012Assignee: Applied Micro Circuits CorporationInventors: Mark Fairhurst, John Dickey
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Publication number: 20090086737Abstract: A Queue Manager (QM) system and method are provided for communicating control messages between processors. The method accepts control messages from a source processor addressed to a destination processor. The control messages are loaded in a first-in first-out (FIFO) queue associated with the destination processor. Then, the method serially supplies loaded control messages to the destination processor from the queue. The messages may be accepted from a plurality of source processors addressed to the same destination processor. The control messages are added to the queue in the order in which they are received. In one aspect, a plurality of parallel FIFO queues may be established that are associated with the same destination processor. Then, the method differentiates the control messages into the parallel FIFO queues and supplies control messages from the parallel FIFO queues in an order responsive to criteria such as queue ranking, weighting, or shaping.Type: ApplicationFiled: September 29, 2007Publication date: April 2, 2009Inventors: Mark Fairhurst, John Dickey
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Publication number: 20090037661Abstract: A system and method are provided for managing transient data in cache memory. The method accepts a segment of data and stores the segment in a cache line. In response to accepting a read-invalidate command for the cache line, the segment is both read from the cache line and the cache line made invalid. If, prior to accepting the read-invalidate command, the segment in the cache line is modified, the modified segment is not stored in a backup storage memory as a result of subsequently accepting the read-invalidate command. In one aspect, the segment is initially identified as transient data, and the read-invalidate command is used in response to identifying the segment as transient data.Type: ApplicationFiled: August 4, 2007Publication date: February 5, 2009Applicant: Applied Micro Circuits CorporationInventor: Mark Fairhurst
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Publication number: 20090037660Abstract: A time-based system and method are provided for controlling the management of cache memory. The method accepts a segment of data, and assigns a cache lock-time with a time duration to the segment. If a cache line is available, the segment is stored (in cache). The method protects the segment stored in the cache line from replacement until the expiration of the lock-time. Upon the expiration of the lock-time, the cache line is automatically made available for replacement. An available cache line is located by determining that the cache line is empty, or by determining that the cache line is available for a replacement segment. In one aspect, the cache lock-time is assigned to the segment by accessing a list with a plurality of lock-times having a corresponding plurality of time duration, and selecting from the list. In another aspect, the lock-time durations are configurable by the user.Type: ApplicationFiled: August 4, 2007Publication date: February 5, 2009Applicant: Applied Micro Circuits CorporationInventor: Mark Fairhurst
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Publication number: 20080137666Abstract: A cut-through system and method are provided for scheduling information in an information distribution device. The method receives a plurality of information streams. A master schedule is created to select messages from the information streams for transfer to a corresponding plurality of remote links. The messages (e.g., packets) may have either a fixed or variable length. The master schedule is responsible for managing a communication link overall maximum bandwidth, and a message bandwidth for each remote link. Concurrently, an underrun schedule is created to select segment rates for a first group of messages destined to corresponding first group of remote links, and manage the message segment rate for the first group of messages. For example, the first group of messages may be destined to remote links that are sensitive to underrun.Type: ApplicationFiled: December 6, 2006Publication date: June 12, 2008Inventors: Mark Fairhurst, Brendan Francis Durkin
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Patent number: D320556Type: GrantFiled: August 25, 1988Date of Patent: October 8, 1991Assignee: Fax-Pax Investments N.V.Inventor: Mark Fairhurst