Patents by Inventor Mark Feuerstraeter

Mark Feuerstraeter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11113402
    Abstract: Methods, systems and apparatuses may provide for technology that includes a system on chip (SoC) having a root of trust and an embedded controller to conduct functional safety operations and non-functional safety operations with respect to the SoC. The technology may also include an enhanced serial peripheral interface (eSPI) coupled to the SoC and the embedded controller, wherein the eSPI is to tunnel communications associated with the functional safety operations between the embedded controller and the root of trust.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: September 7, 2021
    Assignee: Intel Corporation
    Inventors: Mikal Hunsaker, Mark Feuerstraeter, Asad Azam, Zhenyu Zhu, Navtej Singh
  • Publication number: 20190228160
    Abstract: Methods, systems and apparatuses may provide for technology that includes a system on chip (SoC) having a root of trust and an embedded controller to conduct functional safety operations and non-functional safety operations with respect to the SoC. The technology may also include an enhanced serial peripheral interface (eSPI) coupled to the SoC and the embedded controller, wherein the eSPI is to tunnel communications associated with the functional safety operations between the embedded controller and the root of trust.
    Type: Application
    Filed: March 29, 2019
    Publication date: July 25, 2019
    Inventors: Mikal Hunsaker, Mark Feuerstraeter, Asad Azam, Zhenyu Zhu, Navtej Singh
  • Patent number: 7583599
    Abstract: A method and apparatus for transferring data traffic, such as in a SONET/SDH environment, is provided. Two designs are presented, each utilizing a dual device design, where one device performs GFP Framing and the other device performs GFP-T adaptation. The method and apparatus include a first device having a first device FIFO, the first device configured to receive data and assemble data into packets and transfer data across a packet interface when the first device FIFO contains more than N bytes. A second device comprises a second device FIFO, the second device configured to receive data packets from the packet interface and utilize a plurality of thresholds to maintain a quantity of data in the second device FIFO within a predetermined range. Depending on the design employed, control codes, such as 65B_PAD control codes, may be added in the first device under certain conditions to facilitate data transfer.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: September 1, 2009
    Assignee: Intel Corporation
    Inventors: Jing Ling, Vasan Karighattam, Jean-Michel Caia, Edward Pullin, Mark Feuerstraeter, Juan-Carlos Calderon
  • Publication number: 20080037585
    Abstract: An interface and related methods for rate pacing in an Ethernet architecture are described herein.
    Type: Application
    Filed: October 22, 2007
    Publication date: February 14, 2008
    Inventors: Mark Feuerstraeter, Bradley Booth
  • Publication number: 20050058130
    Abstract: A method and apparatus for assigning data traffic classes to virtual channels in communications networks is generally described. In accordance with one embodiment of the invention, a node receiving a data packet including content to initialize a virtual channel on a point-to-point communication link to another node, initializing the virtual channel, based on the content, and mapping a data traffic class to the initialized virtual channel.
    Type: Application
    Filed: July 16, 2004
    Publication date: March 17, 2005
    Inventors: Chris Christ, Mark Feuerstraeter, Han Woojong, Gary Solomon
  • Patent number: 6693550
    Abstract: A visual indicator array has (M×N)/2 pairs of indicator devices arranged in a two-dimensional, linear array having M rows and N columns, where M is an integer greater than or equal to two, and N is an integer greater than or equal to one. The array also includes M/2 enable lines, each of which is connected to all of the indicator devices in two of the M rows to deliver enable signals to the indicator devices in the two rows. Likewise, each of N status lines is connected to all of the indicator devices in one of the N columns. Status information is carried by M×N status signals, and each of N selectors is connected to a corresponding one of the status lines. Each of the N selectors receives M of the status signals and selectively applies the M status signals to the corresponding status line one at a time.
    Type: Grant
    Filed: June 23, 1999
    Date of Patent: February 17, 2004
    Assignee: Intel Corporation
    Inventors: Richard Heiler, Mark Feuerstraeter