Patents by Inventor Mark Forsyth

Mark Forsyth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11255192
    Abstract: The invention relates to a pick sleeve (10) including a head (12) and a shank (14). The head (12) includes a central part (20) and a bearing member (22) which is secured to the central part (20). The bearing member (22) is separable from the central part (20) in order to facilitate removal of the pick sleeve (10) from a holder (38). The invention extends to a tool (50) which is used in the removal of the pick sleeve (10) from the holder (38).
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: February 22, 2022
    Inventors: Gavin James Beard, Mark Forsyth
  • Publication number: 20210003007
    Abstract: The invention relates to a pick sleeve (10) including a head (12) and a shank (14). The head (12) includes a central part (20) and a bearing member (22) which is secured to the central part (20). The bearing member (22) is separable from the central part (20) in order to facilitate removal of the pick sleeve (10) from a holder (38). The invention extends to a tool (50) which is used in the removal of the pick sleeve (10) from the holder (38).
    Type: Application
    Filed: March 14, 2019
    Publication date: January 7, 2021
    Inventors: Gavin James BEARD, Mark FORSYTH
  • Patent number: 5412787
    Abstract: A computer system implementing two levels of translation lookaside buffers (TLBs). The first-level TLBs are small, two-set associative, have a short access time and reside on the CPU chip. The second-level TLBs, on the other hand, are large, direct mapped, and reside in otherwise unused portions of the cache tag RAMs of the instruction and data cache sub-systems. As a result of this arrangement, performance may be improved without limiting the amount of available cache memory for a given implementation. Even if higher capacity memory devices are required for implementing the second-level TLBs in the cache tag RAMs in accordance with the invention, a significant savings over the cost of two sets of smaller devices would still result.
    Type: Grant
    Filed: October 13, 1993
    Date of Patent: May 2, 1995
    Assignee: Hewlett-Packard Company
    Inventors: Mark Forsyth, Patrick Knebel