Abstract: A memory having a two-dimensional array of memory cells organized as a plurality of rows and columns. The memory includes spare rows and columns. A controller in the memory tests the memory at power up and determines if any of the rows or columns are defective. A defective row or column is re-mapped to one of the spare rows or columns, respectively. Data specifying the re-mapping is stored in a separate re-mapping address decode circuit. When an address specifying a memory cell is received by the memory, a conventional address decode circuit decodes the address at the same time the re-mapping decoder searches for a match to the address. If the re-mapping decoder finds the address, it inhibits the conventional decoder and supplies the appropriate column or row select signals. The re-mapping decoder is preferably constructed from a content-addressable memory.

Abstract: A memory having a two-dimensional array of memory cells organized as a plurality of rows and columns. The memory includes spare rows and columns. A controller in the memory tests the memory at power up and determines if any of the rows or columns are defective. A defective row or column is re-mapped to one of the spare rows or columns, respectively. Data specifying the re-mapping is stored in a separate re-mapping address decode circuit. When an address specifying a memory cell is received by the memory, a conventional address decode circuit decodes the address at the same time the re-mapping decoder searches for a match to the address. If the re-mapping decoder finds the address, it inhibits the conventional decoder and supplies the appropriate column or row select signals. The re-mapping decoder is preferably constructed from a content-addressable memory.

Abstract: A reconfigurable memory having M bit lines and a plurality of row lines, where M>1. The memory includes an array of memory storage cells, each memory storage cell storing a data value. The data value is read from or into the storage cells by coupling that data value to one of the bit lines in response to a row control signal on one of the row lines. A row select circuit generates the row control signal on one of the row lines in response to a row address being coupled to the row select circuit. The row select circuit includes a memory for storing a mapping of the row addresses to the row lines that determines which of the row lines is selected for each possible value of the row address.

Abstract: A memory that includes a plurality of storage blocks. Each block has a plurality of storage cells constructed from a storage element and an isolation transistor. The storage cells in a block are organized as a plurality of rows and column units. Each column unit includes a first bit line and a plurality of the memory cells connected to the first bit line by the isolation transistors in those memory cells. The memory also includes a first multiplexer connected to a plurality of the first bit lines in a first one of the memory blocks, the first multiplexer connecting one of the first bit lines to a first conductor in response to one or more first multiplexer control signals. The first multiplexer is located adjacent to the storage block containing first bit lines connected thereto. The first conductor is connected to a sense amplifier for reading the contents of the storage cells. The sense amplifier may be located adjacent to the first multiplexer or at a remote location relative to the storage block.

Abstract: A reconfigurable memory having M bit lines and a plurality of row lines, where M>1. The memory includes an array of memory storage cells, each memory storage cell storing a data value. The data value is read from or into the storage cells by coupling that data value to one of the bit lines in response to a row control signal on one of the row lines. A row select circuit generates the row control signal on one of the row lines in response to a row address being coupled to the row select circuit. The row select circuit includes a memory for storing a mapping of the row addresses to the row lines that determines which of the row lines is selected for each possible value of the row address. The memory includes a plurality of sense amplifiers, one such sense amplifier being connected to each of the bit lines for measuring a signal value on that bit line. A controller that is part of the memory tests the memory storage cells both at power up and run time to detect defective memory storage cells.

Abstract: A variable phase shift network (420) for a phase quadrature signal generator (320, 370) includes a variable current controller (909), a first NPN transistor (801) and a second NPN transistor (802). The variable phase shift network (420) produces a first quadrature input signal (830), a second quadrature input signal (834), a first quadrature output signal (821) and a second quadrature output signal (826) responsive to receiving a first differential input signal (919) and a second differential input signal (925).