Patents by Inventor Mark Fredrickson

Mark Fredrickson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240140220
    Abstract: An electric vehicle supply equipment may include electrical power transfer circuitry having a power input and a power output. An electric vehicle supply equipment may include a recipient connector connected to the power output and configured to interconnect with a recipient charge port of a recipient vehicle. An electric vehicle supply equipment may include a donor connector connected to the power input and configured to interconnect with a donor charge port of a donor vehicle, wherein the donor connector has one or more electrical attributes that distinguish the donor connector from the recipient connector.
    Type: Application
    Filed: October 26, 2023
    Publication date: May 2, 2024
    Inventors: Jeffrey KIKO, Don BIZON, Anthony RASCHILLA, Mark FREDRICKSON, Stephen KOULIANOS, Boris BORIN
  • Publication number: 20230299512
    Abstract: An electrical connector assembly includes a connector housing defining a cavity and an opening providing access to the cavity, first and second direct current (DC) terminals disposed within the cavity, and first and second busbars electrically and mechanically attached directly to the first and second DC terminals respectively. The first and second busbars each have a rectangular cross section and wherein the first and second busbars extend through the opening such that portions of the first and second busbars are outside of the connector housing. A method of manufacturing an electrical connector assembly is also provided.
    Type: Application
    Filed: March 15, 2023
    Publication date: September 21, 2023
    Inventors: Don E. Bizon, Thomas Mathews, Mark Fredrickson, John Pechatsko, Boris Borin
  • Patent number: 11697353
    Abstract: An electrical connector includes a plurality of cylindrical electrical terminals connected to ends of a plurality of first electrical cables, a housing defining a plurality of housing terminal cavities in which the plurality of cylindrical electrical terminals is disposed, and a cover attached to the housing having a plurality of cover cavities that is axially aligned with the plurality of housing terminal cavities. The plurality of cover cavities is configured to receive the plurality of cylindrical electrical terminals as it is inserted within the plurality of housing terminal cavities.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: July 11, 2023
    Assignee: APTIV TECHNOLOGIES LIMITED
    Inventors: Thomas Mathews, William C. Lovitz, Mark Fredrickson, Ronald A. Puhl
  • Publication number: 20230085351
    Abstract: A power inlet connector assembly configured for use in charging an electrical vehicle includes a housing subassembly containing a plurality of direct current (DC) electrical terminals configured to mate with corresponding direct current electrical terminals of a power outlet connector of an electrical vehicle charging device external to the electrical vehicle and a cover subassembly configured to be connected and disconnected from the housing subassembly. The cover subassembly contains electrical bus bars and alternating current (AC) electrical terminals having first ends configured to mate with corresponding AC electrical terminals of a power outlet connector of an electrical vehicle charging device. The electrical bus bars are configured to be connected and disconnected with the DC electrical terminals and the AC electrical terminals are configured to be inserted and removed from terminal cavities defined by the housing subassembly.
    Type: Application
    Filed: September 7, 2022
    Publication date: March 16, 2023
    Inventors: Thomas Mathews, Don E. Bizon, William C. Lovitz, Troy A. Iler, Mark Fredrickson
  • Publication number: 20220393372
    Abstract: An electrical connector assembly includes a connector housing in which a pair of electrically conductive busbars are disposed, a metallic cooling plate in thermal communication with major surfaces of the pair of electrically conductive busbars, and a dielectric structure that is configured to prevent electrical contact between the pair of electrically conductive busbars and the cooling plate.
    Type: Application
    Filed: June 3, 2022
    Publication date: December 8, 2022
    Inventors: Thomas Mathews, Mark Fredrickson
  • Patent number: 11263332
    Abstract: A computer system, processor, and method for processing information is disclosed that includes watching logical operations to detect unauthorized attempts to access a register, and taking evasive action in response to detecting unauthorized attempts to access the register. In an embodiment, the register is a hidden, secret, restricted, or undocumented register, and the method further includes, in response to unauthorized attempts to access the secret register, locking the contents of the secret register. The evasive action may include one or more of interrupting the operations of the processor; causing the processor to shut-down, malfunction, lock, self-destruct; no longer providing read or write permission or access to the register; releasing data disguised to look like the real register data while not releasing the real data; and combinations thereof.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: March 1, 2022
    Assignee: International Business Machines Corporation
    Inventors: Mark Fredrickson, Chad Albertson, Scott D. Frei, David G. Wheeler
  • Publication number: 20220055490
    Abstract: An electrical connector includes a plurality of cylindrical electrical terminals connected to ends of a plurality of first electrical cables, a housing defining a plurality of housing terminal cavities in which the plurality of cylindrical electrical terminals is disposed, and a cover attached to the housing having a plurality of cover cavities that is axially aligned with the plurality of housing terminal cavities. The plurality of cover cavities is configured to receive the plurality of cylindrical electrical terminals as it is inserted within the plurality of housing terminal cavities.
    Type: Application
    Filed: August 21, 2020
    Publication date: February 24, 2022
    Inventors: Thomas Mathews, William C. Lovitz, Mark Fredrickson, Ronald A. Puhl
  • Publication number: 20200042730
    Abstract: A computer system, processor, and method for processing information is disclosed that includes watching logical operations to detect unauthorized attempts to access a register, and taking evasive action in response to detecting unauthorized attempts to access the register. In an embodiment, the register is a hidden, secret, restricted, or undocumented register, and the method further includes, in response to unauthorized attempts to access the secret register, locking the contents of the secret register. The evasive action may include one or more of interrupting the operations of the processor; causing the processor to shut-down, malfunction, lock, self-destruct; no longer providing read or write permission or access to the register; releasing data disguised to look like the real register data while not releasing the real data; and combinations thereof.
    Type: Application
    Filed: July 31, 2018
    Publication date: February 6, 2020
    Inventors: Mark Fredrickson, Chad Albertson, Scott D. Frei, David G. Wheeler
  • Publication number: 20080070822
    Abstract: The present invention includes a composition comprising an enriched mixture of ?-sulfofatty acid esters. Increasing the concentration of specific chain length ?-sulfofatty acid esters, relative to the proportions of the other chain lengths, allows the detergent compositions to exhibit an improved cleaning performance while simultaneously cleaning a wide variety of materials.
    Type: Application
    Filed: July 19, 2007
    Publication date: March 20, 2008
    Applicant: Huish Detergents, Incorporated
    Inventors: Paul Huish, Laurie Jensen, Pule Libe, Mark Fredrickson
  • Publication number: 20080052472
    Abstract: In a first aspect, a first method of reducing command processing latency while maintaining memory coherence is provided. The first method includes the steps of (1) providing a memory map including memory addresses available to a system; and (2) arranging the memory addresses into a plurality of groups. At least one of the groups does not require the system, in response to a command that requires access to a memory address in the group from a bus unit, to get permission from all remaining bus units included in the system to maintain memory coherence. Numerous other aspects are provided.
    Type: Application
    Filed: August 29, 2007
    Publication date: February 28, 2008
    Inventors: Jeffrey Brown, Scott Clark, Mark Fredrickson, Charles Johns, David Krolak
  • Publication number: 20070260949
    Abstract: An apparatus, program product and method utilize a clustering algorithm based upon trading propensity to generate assignments of circuit elements to clusters or groups to optimize a spatial distribution of the plurality of clusters. For example, trading propensity-based clustering may be used to assign circuit elements such as scan-enabled latches to individual scan chains to optimize the layout of the scan chains in a scan architecture for an integrated circuit design.
    Type: Application
    Filed: February 7, 2006
    Publication date: November 8, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark Fredrickson, Chad McBride
  • Publication number: 20070186052
    Abstract: In a first aspect, a first method of reducing command processing latency while maintaining memory coherence is provided. The first method includes the steps of (1) providing a memory map including memory addresses available to a system; and (2) arranging the memory addresses into a plurality of groups. At least one of the groups does not require the system, in response to a command that requires access to a memory address in the group from a bus unit, to get permission from all remaining bus units included in the system to maintain memory coherence. Numerous other aspects are provided.
    Type: Application
    Filed: February 7, 2006
    Publication date: August 9, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey Brown, Scott Clark, Mark Fredrickson, Charles Johns, David Krolak
  • Publication number: 20070186204
    Abstract: An apparatus, program product and method automatically back annotate a functional definition of a circuit design based upon the physical layout generated from the functional definition. A circuit design may be back annotated, for example, by generating a plurality of assignments between a plurality of circuit elements in the circuit design and a plurality of signals defined for the circuit design using a physical definition of the circuit design that has been generated from the functional definition, and modifying the functional definition of the circuit design to incorporate the plurality of assignments into the functional definition.
    Type: Application
    Filed: February 7, 2006
    Publication date: August 9, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark Fredrickson, Glen Handlogten, Chad McBride
  • Publication number: 20070186199
    Abstract: An apparatus, program product and method utilize heuristic clustering to generate assignments of circuit elements to clusters or groups to optimize a desired spatial locality metric. For example, circuit elements such as scan-enabled latches may be assigned to individual scan chains using heuristic clustering to optimize the layout of the scan chains in a scan architecture for a circuit design.
    Type: Application
    Filed: February 7, 2006
    Publication date: August 9, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark Fredrickson, Glen Handlogten, Chad McBride
  • Publication number: 20070168797
    Abstract: Methods, apparatus, and computer program product are provided for designing logic scan chains for matching gated portions of a clock tree. A clock tree includes a plurality of sections, each section including a gate receiving inputs of a global clock and a chain-specific clock control signal for a particular scan chain. A plurality of scan chains is defined, each including a plurality of latches. Each scan chain latch is connected to a corresponding chain-specific clock tree section.
    Type: Application
    Filed: July 28, 2005
    Publication date: July 19, 2007
    Applicant: International Business Machines Corporation
    Inventors: Mark Fredrickson, Glen Handlogten, Steven Jones, Chad McBride
  • Publication number: 20070101221
    Abstract: A method, apparatus and computer program product are provided for implementing scan-chain-specific control signals as an integral part of a scan chain. A scan input vector including scan data input and a scan control signal is applied to a register latch that forms the scan chain. The register latch includes a logic gate for combining a global clock control (THOLD) signal and the scan control signal. The scan control signal is routed around the register latch and including in a scan output vector including scan data output. Chain-specific control signals are eliminated from a clock control signal distribution tree used with the scan chain of the invention.
    Type: Application
    Filed: November 3, 2005
    Publication date: May 3, 2007
    Applicant: International Business Machines Corporation
    Inventors: Mark Fredrickson, Scott Frei, Steven Jones
  • Publication number: 20070073949
    Abstract: A fair hierarchical arbiter comprises a number of arbitration mechanisms, each arbitration mechanism forwarding winning requests from requestors in round robin order by requestor. In addition to the winning requests, each arbitration mechanism forwards valid request bits, the valid request bits providing information about which requestor originated a current winning request, and, in some embodiments, about how many separate requesters are arbitrated by that particular arbitration mechanism. The fair hierarchical arbiter outputs requests from the total set of separate requestors in a round robin order.
    Type: Application
    Filed: September 29, 2005
    Publication date: March 29, 2007
    Applicant: International Business Machines Corporation
    Inventors: Mark Fredrickson, David Krolak
  • Patent number: 6683039
    Abstract: The present invention includes a composition comprising an enriched mixture of &agr;-sulfofatty acid esters. Increasing the concentration of specific chain length &agr;-sulfofatty acid esters, relative to the proportions of the other chain lengths, allows the detergent compositions to exhibit an improved cleaning performance while simultaneously cleaning a wide variety of materials.
    Type: Grant
    Filed: May 19, 2000
    Date of Patent: January 27, 2004
    Assignee: Huish Detergents, Inc.
    Inventors: Paul Danton Huish, Laurie A. Jensen, Pule B. Libe, Mark Fredrickson