Patents by Inventor Mark Fullerton

Mark Fullerton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10804906
    Abstract: Adaptive clocking schemes for synchronized on-chip functional blocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example. In embodiments, the clocking schemes allow for the capacity utilization of a logic path to be increased.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: October 13, 2020
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Paul Penzes, Mark Fullerton
  • Publication number: 20180309455
    Abstract: Adaptive clocking schemes for synchronized on-chip functional blocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example. In embodiments, the clocking schemes allow for the capacity utilization of a logic path to be increased.
    Type: Application
    Filed: June 25, 2018
    Publication date: October 25, 2018
    Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Paul PENZES, Mark FULLERTON
  • Patent number: 10033391
    Abstract: Adaptive clocking schemes for synchronized on-chip functional blocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example. In embodiments, the clocking schemes allow for the capacity utilization of a logic path to be increased.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: July 24, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Paul Penzes, Mark Fullerton
  • Publication number: 20160226498
    Abstract: Adaptive clocking schemes for synchronized on-chip functional blocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example. In embodiments, the clocking schemes allow for the capacity utilization of a logic path to be increased.
    Type: Application
    Filed: April 11, 2016
    Publication date: August 4, 2016
    Applicant: Broadcom Corporation
    Inventors: Paul Penzes, Mark Fullerton
  • Patent number: 9407272
    Abstract: Systems and methods are presented for reducing the impact of high load and aging on processor cores in a processor. A Power Management Unit (PMU) can monitor aging, temperature, and increased load on the processor cores. The PMU instructs the processor to take action such that aging, temperature, and/or increased load are approximately evenly distributed across the processor cores, so that the processor can continue to efficiently process instructions.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: August 2, 2016
    Assignee: Broadcom Corporation
    Inventors: Paul Penzes, Mark Fullerton, Hwisung Jung, John Walley, Tim Sippel, Love Kothari
  • Patent number: 9312862
    Abstract: Adaptive clocking schemes for synchronized on-chip functional blocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example. In embodiments, the clocking schemes allow for the capacity utilization of a logic path to be increased.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: April 12, 2016
    Assignee: Broadcom Corporation
    Inventors: Paul Penzes, Mark Fullerton
  • Patent number: 9225343
    Abstract: An electronics device is disclosed that reduces latency resulting from communication between a first electronics component operating based on a fast clock and a second electronics component operating based on a slow clock reduces communication latency. When transferring the data from the first component to the second, the data is written into a buffer using the first clock, and then extracted by the second component using the second clock. Alternatively, when transferring the data from the second component to the first component, the first component reads the data from the second component and monitors whether the data was extracted during a relevant edge of the second clock signal, in which case the first component again extracts the data from the second component.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: December 29, 2015
    Assignee: Broadcom Corporation
    Inventors: Love Kothari, Mark Fullerton, Rajesh Rajan, Veronica Alarcon
  • Patent number: 9209816
    Abstract: Certain semiconductor processes provide for the use of multiple different types of transistors with different threshold voltages in a single IC. It can be shown that in certain ones of these semiconductor processes, the speed at which high threshold transistors can operate at decreases with decreasing temperature. Thus, the overall processing speed of an IC that implements high threshold transistors is often limited by the lowest temperature at which the IC is designed (or guaranteed) to properly function. Embodiments of a system and method that overcome this deficiency by “pre-heating” the IC (or at least portions of the IC that implement the high threshold transistors) such that the IC can operate at a frequency (once pre-heated) higher than what would otherwise be possible for a given, minimum temperature at which the IC is designed (or guaranteed) to properly function at are provided.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: December 8, 2015
    Assignee: Broadcom Corporation
    Inventors: Paul Penzes, Mark Fullerton
  • Patent number: 9043615
    Abstract: In an embodiment, an apparatus includes a cryptographic processor within a wireless device. The cryptographic processor includes at least one cryptographic unit. The cryptographic processor also includes a nonvolatile memory to store one or more microcode instructions, wherein at least one of the one or more microcode instructions is related to a sensitive operation. The cryptographic processor also includes a controller to control execution of the one or more microcode instructions by the at least one cryptographic unit, wherein the controller is to preclude execution of the sensitive operation if the apparatus is within an untrusted state.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: May 26, 2015
    Assignee: Intel Corporation
    Inventors: Mark Fullerton, Moinul Khan, David Wheeler, John Brizek, Anitha Kona
  • Publication number: 20140359323
    Abstract: A system and method for closed loop power supply control in large, multiple processor installations are provided.
    Type: Application
    Filed: September 24, 2010
    Publication date: December 4, 2014
    Applicant: SMOOTH-STONE, INC. C/O BARRY EVANS
    Inventors: Mark Fullerton, Christopher Carl Ott, Mark Bradley Davis, Arnold Thomas Schnell
  • Publication number: 20140215252
    Abstract: Systems and methods are provided for efficiently managing power among system components. In an embodiment, a power manager receives information from subsystems and determines which subsystem components will require power to perform upcoming tasks. Based on this received information, the power manager can power on and power down individual subsystem components. Systems and methods according to embodiments of the present disclosure enable a cache of a subsystem to be powered on without requiring a power-up of every component of the subsystem. Thus, disclosed systems and methods enable a first subsystem to snoop into a cache of a second subsystem without requiring a full power-up of the second subsystem.
    Type: Application
    Filed: September 13, 2013
    Publication date: July 31, 2014
    Applicant: Broadcom Corporation
    Inventors: Mark FULLERTON, Ronak PATEL, Timothy CHEN, Lei YU
  • Publication number: 20140215233
    Abstract: Systems and methods are provided for efficiently powering down elements and buses of a system without negatively impacting traffic. A power manager receives information from subsystems and determines whether a particular subsystem or bus can be powered down. The power manager sends a message to a subsystem when the subsystem or bus can be safely powered down. Blocker modules are coupled to buses, and the blocker modules respond with an error message if a subsystem attempts to send data over an inactive bus.
    Type: Application
    Filed: September 13, 2013
    Publication date: July 31, 2014
    Applicant: Broadcom Corporation
    Inventors: Mark Fullerton, Lance Flake, Timothy Chen, Lei Yu, Anru Wang, Nirav Pravinkumar Dagli, Ronak Patel
  • Patent number: 8782314
    Abstract: Embodiments include a system and method for an interrupt controller that propagates interrupts to a subsystem in a system-on-a-chip (SOC). Interrupts are provided to an interrupt controller that controls access of interrupts to a particular subsystem in the SOC that includes multiple subsystems. Each subsystem in the SOC generates multiple interrupts to other subsystems in the SOC. The interrupt controller processes multiple interrupts and generates an interrupt output. The interrupt output is then transmitted to a particular subsystem.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: July 15, 2014
    Assignee: Broadcom Corporation
    Inventors: Love Kothari, Mark Fullerton
  • Publication number: 20140189371
    Abstract: In an embodiment, an apparatus includes a cryptographic processor within a wireless device. The cryptographic processor includes at least one cryptographic unit. The cryptographic processor also includes a nonvolatile memory to store one or more microcode instructions, wherein at least one of the one or more microcode instructions is related to a sensitive operation. The cryptographic processor also includes a controller to control execution of the one or more microcode instructions by the at least one cryptographic unit, wherein the controller is to preclude execution of the sensitive operation if the apparatus is within an untrusted state.
    Type: Application
    Filed: March 4, 2014
    Publication date: July 3, 2014
    Inventors: Mark Fullerton, Moinul Khan, David Wheeler, John Brizek, Anitha Kona
  • Patent number: 8756406
    Abstract: In one embodiment the present invention includes a method and apparatus for enabling a main core and one or more co-processors to operate in a de-coupled mode, thereby facilitating the execution of two or more instruction threads in parallel. A co-processor, according to an embodiment of the invention, has a coupling manager including a loop buffer for storing instructions which can be independently fetched and executed by the co-processor when operating in de-coupled mode. In addition, the coupling manager includes a loop descriptor and a counter/condition descriptor. The loop descriptor and condition descriptor work in conjunction with one another to determine what, if any, action should be taken when a co-processor is in a particular processing state, for example, as indicated by a counter keeping track of loop processing.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: June 17, 2014
    Assignee: Marvell International Ltd.
    Inventors: Moinul Khan, Mark Fullerton, Arthur Miller, Anitha Kona
  • Patent number: 8700972
    Abstract: Embodiments provide an adaptive memory that allows for low voltage modes of operation. In the low voltage modes of operation, the supply voltage provided to the memory is reduced below Vcc(min), which allows for significant savings in the power consumption of circuit components (e.g., the CPU) whose minimum voltage is dictated by Vcc(min). According to further embodiments, the memory can be configured dynamically according to various configurations depending on desired power savings (e.g., target Vcc(min)) and/or performance requirements (e.g., reliability, cache size requirement, etc.).
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: April 15, 2014
    Assignee: Broadcom Corporation
    Inventors: Paul Penzes, Mark Fullerton, Ajat Hukkoo, John Walley
  • Publication number: 20140028344
    Abstract: Certain semiconductor processes provide for the use of multiple different types of transistors with different threshold voltages in a single IC. It can be shown that in certain ones of these semiconductor processes, the speed at which high threshold transistors can operate at decreases with decreasing temperature. Thus, the overall processing speed of an IC that implements high, threshold transistors is often limited by the lowest temperature at which the IC is designed (or guaranteed) to properly function. Embodiments of a system and method that overcome this deficiency by “pre-heating” the IC (or at least portions of the IC that implement the high threshold transistors) such that the IC can operate at a frequency (once pre-heated) higher than what would otherwise be possible for a given minimum temperature at which the IC is designed or guaranteed) to properly function at are provided.
    Type: Application
    Filed: September 30, 2013
    Publication date: January 30, 2014
    Applicant: Broadcom Corporation
    Inventors: Paul Penzes, Mark Fullerton
  • Patent number: 8575993
    Abstract: Certain semiconductor processes provide for the use of multiple different types of transistors with different threshold voltages in a single IC. It can be shown that in certain ones of these semiconductor processes, the speed at which high threshold transistors can operate at decreases with decreasing temperature. Thus, the overall processing speed of an IC that implements high threshold transistors is often limited by the lowest temperature at which the IC is designed (or guaranteed) to properly function. Embodiments of a system and method that overcome this deficiency by “pre-heating” the IC (or at least portions of the IC that implement the high threshold transistors) such that the IC can operate at a frequency (once pre-heated) higher than what would otherwise be possible for a given, minimum temperature at which the IC is designed (or guaranteed) to properly function at are provided.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: November 5, 2013
    Assignee: Broadcom Corporation
    Inventors: Paul Penzes, Mark Fullerton
  • Publication number: 20130117626
    Abstract: Embodiments provide an adaptive memory that allows for low voltage modes of operation. In the low voltage modes of operation, the supply voltage provided to the memory is reduced below Vcc(min), which allows for significant savings in the power consumption of circuit components (e.g., the CPU) whose minimum voltage is dictated by Vcc(min). According to further embodiments, the memory can be configured dynamically according to various configurations depending on desired power savings (e.g., target Vcc(min)) and/or performance requirements (e.g., reliability, cache size requirement, etc.).
    Type: Application
    Filed: November 4, 2011
    Publication date: May 9, 2013
    Applicant: Broadcom Corporation
    Inventors: Paul PENZES, Mark Fullerton, Ajat Hukkoo, John Walley
  • Publication number: 20130082764
    Abstract: An apparatus and method are disclosed to combine pad functionality in an integrated circuit. A power, ground, or signal pad is connected to a power, ground, or signal source, respectively. The power, ground, or signal pad is additionally connected to an additional signal source, such as automatic test equipment in a testing environment. By temporarily disconnecting either the power, ground, or signal source, from the functional block within the integrated circuit to which the source is delivered, the same pad may pass in another signal to other portions of the integrated circuit. In the alternative, the same pad may pass in another signal to other portions of the integrated circuit without disconnecting the original signal by coupling the additional signal over the original signal. Further, combining pad functionality enables reuse of an input pad as an output pad for signals originating from within the integrated circuit.
    Type: Application
    Filed: September 30, 2011
    Publication date: April 4, 2013
    Applicant: BROADCOM CORPORATION
    Inventors: Paul Penzes, Love Kothari, Ajat Hukkoo, Mark Fullerton, Veronica Alarcon, Zhongmin Zhang, Kerry Alan Thompson, Russell Radke