Patents by Inventor Mark G. Atkins

Mark G. Atkins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7925728
    Abstract: A series of state transitions is indicative of performance of hardware service actions. A transition from, for instance, a disconnected state to a connected state for a hardware component is indicative of performance of a service action for the hardware component. Detection of this transition is automatic.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: April 12, 2011
    Assignee: International Business Machines Corporation
    Inventors: Mark G. Atkins, John Divirgilio, Jay R. Herring, LeRoy R. Lundin, Nicholas P. Rash, Karen F. Rash, legal representative
  • Patent number: 7872982
    Abstract: A system, method, and computer-readable medium for detecting errors on a network. According to a preferred embodiment of the present invention, a network error manager retrieves a network topology from a master subnet manager, wherein the network includes a collection of devices coupled by a first interconnect type. When a connectivity failure is detected in the first interconnect type, the network error manager receives from the master subnet manager at least one event notification via a second interconnect type. An error log analysis component identifies at least one device among the collection of devices as a possible cause of the connectivity failure in the first interconnect type. The network error manager retrieves events from at least one device among the collection of devices that can influence a state of the first interconnect type.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: January 18, 2011
    Assignee: International Business Machines Corporation
    Inventors: Mark G. Atkins, Michal B. Cohen, John W. Doxtader, Chetan Mehta, Patrick J. Sugrue
  • Publication number: 20080080384
    Abstract: A system, method, and computer-readable medium for detecting errors on a network. According to a preferred embodiment of the present invention, a network error manager retrieves a network topology from a master subnet manager, wherein the network includes a collection of devices coupled by a first interconnect type. When a connectivity failure is detected in the first interconnect type, the network error manager receives from the master subnet manager at least one event notification via a second interconnect type. An error log analysis component identifies at least one device among the collection of devices as a possible cause of the connectivity failure in the first interconnect type. The network error manager retrieves events from at least one device among the collection of devices that can influence a state of the first interconnect type.
    Type: Application
    Filed: October 2, 2006
    Publication date: April 3, 2008
    Inventors: Mark G. Atkins, Michal B. Cohen, John W. Doxtader, Chetan Mehta, Patrick J. Sugrue
  • Patent number: 6618815
    Abstract: Apparatus for synchronizing time-of-day events across a plurality of neighboring processing nodes organized in a distributed parallel processing system with each processing node including a time-of-day (TOD) incrementor. The TOD incrementor of each processing node is coupled to a local oscillator in the processing node running at a preselected frequency to increment locally the TOD incrementor. A controller determines one of the processing nodes as the master processing node by transmitting an initialization packet to the selected processing node, and transmits a set TOD service packet to the selected master processing node. The master processing node includes a broadcast generator that broadcasts TOD update packets to neighboring processing nodes. A register in the master processing node counts a multiple of the preselected frequency.
    Type: Grant
    Filed: February 29, 2000
    Date of Patent: September 9, 2003
    Assignee: International Business Machines Corporation
    Inventors: Mark G. Atkins, Jay R. Herring
  • Patent number: 6021442
    Abstract: A method, associated apparatus and program product for partitioning a plurality of interconnection elements among disjoint partitions of processors in a computer system so as to interconnect the processors within each of the disjoint partitions, and to isolate the processors in each interconnected partition from processors in the other partitions. The interconnection elements may be arranged into groups including node coupling elements and link coupling elements and in larger systems may include intermediate groups having intermediate coupling elements.
    Type: Grant
    Filed: July 17, 1997
    Date of Patent: February 1, 2000
    Assignee: International Business Machines Corporation
    Inventors: Aruna V. Ramanan, Mark Gurevich, Leroy R. Lundin, David G. Folsom, Kevin J. Reilly, Mark G. Atkins, Robert F. Bartfai
  • Patent number: 5887184
    Abstract: A method, associated apparatus and program product for partitioning a plurality of interconnection elements among disjoint partitions of processors in a computer system so as to interconnect the processors within each of the disjoint partitions, and to isolate the processors in each interconnected partition from processors in the other partitions. The interconnection elements may be arranged into groups including node coupling elements and link coupling elements and in larger systems may include intermediate groups having intermediate coupling elements.
    Type: Grant
    Filed: July 17, 1997
    Date of Patent: March 23, 1999
    Assignee: International Business Machines Corporation
    Inventors: Aruna V. Ramanan, Mark Gurevich, Leroy R. Lundin, David G. Folsom, Kevin J. Reilly, Mark G. Atkins, Robert F. Bartfai
  • Patent number: 5884090
    Abstract: A method, associated apparatus and program product for partitioning a plurality of interconnection elements among disjoint partitions of processors in a computer system so as to interconnect the processors within each of the disjoint partitions, and to isolate the processors in each interconnected partition from processors in the other partitions. The interconnection elements may be arranged into groups including node coupling elements and link coupling elements and in larger systems may include intermediate groups having intermediate coupling elements.
    Type: Grant
    Filed: July 17, 1997
    Date of Patent: March 16, 1999
    Assignee: International Business Machines Corporation
    Inventors: Aruna V. Ramanan, Mark Gurevich, Leroy R. Lundin, David G. Folsom, Kevin J. Reilly, Mark G. Atkins, Robert F. Bartfai